Arithmetic logic unit

The inputs to an ALU are the data to be operated on, called operands, and a code indicating the operation to be performed (opcode); the ALU's output is the result of the performed operation. In many designs, the ALU also has status inputs or outputs, or both, which convey information about a previous operation or the current operation, respectively, between the ALU and external status registers.

Signals

An ALU has a variety of input and output nets, which are the electrical conductors used to convey digital signals between the ALU and external circuitry. When an ALU is operating, external circuits apply signals to the ALU inputs and, in response, the ALU produces and conveys signals to external circuitry via its outputs.

Data

A basic ALU has three parallel data buses consisting of two input operands (A and B) and a result output (Y). Each data bus is a group of signals that conveys one binary integer number. Typically, the A, B and Y bus widths (the number of signals comprising each bus) are identical and match the native word size of the external circuitry (e.g., the encapsulating CPU or other processor).

Opcode

The opcode input is a parallel bus that conveys to the ALU an operation selection code, which is an enumerated value that specifies the desired arithmetic or logic operation to be performed by the ALU. The opcode size (its bus width) determines the maximum number of distinct operations the ALU can perform; for example, a four-bit opcode can specify up to sixteen different ALU operations. Generally, an ALU opcode is not the same as a machine language instruction, though in some cases it may be directly encoded as a bit field within such instructions.

Status

Outputs

The status outputs are various individual signals that convey supplemental information about the result of the current ALU operation. General-purpose ALUs commonly have status signals such as:

Carry-out, which conveys the carry resulting from an addition operation, the borrow resulting from a subtraction operation, or the overflow bit resulting from a binary shift operation.
Zero, which indicates all bits of Y are logic zero.
Negative, which indicates the result of an arithmetic operation is negative.
Overflow, which indicates the result of an arithmetic operation has exceeded the numeric range of Y.
Parity, which indicates whether an even or odd number of bits in Y are logic one.

Inputs

The status inputs allow additional information to be made available to the ALU when performing an operation. Typically, this is a single "carry-in" bit that is the stored carry-out from a previous ALU operation.

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Circuit operation

An ALU is a combinational logic circuit, meaning that its outputs will change asynchronously in response to input changes. In normal operation, stable signals are applied to all of the ALU inputs and, when enough time (known as the "propagation delay") has passed for the signals to propagate through the ALU circuitry, the result of the ALU operation appears at the ALU outputs. The external circuitry connected to the ALU is responsible for ensuring the stability of ALU input signals throughout the operation, and for allowing sufficient time for the signals to propagate through the ALU circuitry before sampling the ALU outputs.

In general, external circuitry controls an ALU by applying signals to the ALU inputs. Typically, the external circuitry employs sequential logic to generate the signals that control ALU operation. The external sequential logic is paced by a clock signal of sufficiently low frequency to ensure enough time for the ALU outputs to settle under worst-case conditions (i.e., conditions resulting in the maximum possible propagation delay).

For example, a CPU starts an addition operation by routing the operands from their sources (typically processor registers) to the ALU's operand inputs, while simultaneously applying a value to the ALU's opcode input that configures it to perform an addition operation. At the same time, the CPU enables the destination register to store the ALU output (the resulting sum from the addition operation) upon operation completion. The ALU's input signals, which are held stable until the next clock, are allowed to propagate through the ALU and to the destination register while the CPU waits for the next clock. When the next clock arrives, the destination register stores the ALU result and, since the ALU operation has completed, the ALU inputs may be set up for the next ALU operation.

Functions

A number of basic arithmetic and bitwise logic functions are commonly supported by ALUs. Basic, general purpose ALUs typically include these operations in their repertoires:

Arithmetic operations

Add: A and B are summed and the sum appears at Y and carry-out.
Add with carry: A, B and carry-in are summed and the sum appears at Y and carry-out.
Subtract: B is subtracted from A (or vice versa) and the difference appears at Y and carry-out. For this function, carry-out is effectively a "borrow" indicator. This operation may also be used to compare the magnitudes of A and B; in such cases the Y output may be ignored by the processor, which is only interested in the status bits (particularly zero, negative, and carry) that result from the operation.
Subtract with borrow: B is subtracted from A (or vice versa) with borrow (carry-in) and the difference appears at Y and carry-out (borrow out).
Two's complement: The negative of A (or B) appears at Y in two's complement form.
Increment: A (or B) is increased by one and the resulting value appears at Y.
Decrement: A (or B) is decreased by one and the resulting value appears at Y.

Bitwise logical operations

AND: the bitwise AND of A and B appears at Y. AND may also be used to TEST bits. In this case, the result would not be stored; only the status bits (particularly zero and negative) would be recorded.
OR: the bitwise OR of A and B appears at Y.
Exclusive-OR: the bitwise XOR of A and B appears at Y.
Ones' complement: all bits of A (or B) are inverted and appear at Y.

Bit shift operations

ALU shift operations cause operand A (or B) to shift left or right (depending on the opcode) and the shifted operand appears at Y. Simple ALUs typically can shift the operand by only one bit position, whereas more complex ALUs employ barrel shifters that allow them to shift the operand by an arbitrary number of bits in one operation. In all single-bit shift operations, the bit shifted out of the operand appears on carry-out; the value of the bit shifted into the operand depends on the type of shift.

Arithmetic shift: the operand is treated as a two's complement integer, meaning that the most significant bit is a "sign" bit and is preserved.
Logical shift: a logic zero is shifted into the operand. This is used to shift unsigned integers.
Rotate: the operand is treated as a circular buffer of bits in which its least and most significant bits are effectively adjacent.
Rotate through carry: the carry bit and operand are collectively treated as a circular buffer of bits.

Other operations

Pass through: all bits of A (or B) appear unmodified at Y. This operation is typically used to determine the parity of the operand or whether it is zero or negative, or to copy the operand to a processor register.

Applications

Status usage

Upon completion of each ALU operation, the ALU's status output signals are usually stored in external registers to make them available for future ALU operations (e.g., to implement multiple-precision arithmetic) and for controlling conditional branching. The bit registers that store the status output signals are often collectively treated as a single, multi-bit register, which is referred to as the "status register" or "condition code register".

Depending on the ALU operation being performed, some status register bits may be changed and others may be left unmodified. For example, in bitwise logical operations such as AND and OR, the carry status bit is typically not modified as it is not relevant to such operations.

In CPUs, the stored carry-out signal is usually connected to the ALU's carry-in net. This facilitates efficient propagation of carries (which may represent addition carries, subtraction borrows, or shift overflows) when performing multiple-precision operations, as it eliminates the need for software-management of carry propagation (via conditional branching, based on the carry status bit).

Operand and result data paths

The sources of ALU operands and destinations of ALU results depend on the architecture of the encapsulating processor and the operation being performed. Processor architectures vary widely, but in general-purpose CPUs, the ALU typically operates in conjunction with a register file (array of processor registers) or accumulator register, which the ALU frequently uses as both a source of operands and a destination for results. To accommodate other operand sources, multiplexers are commonly used to select either the register file or alternative ALU operand sources as required by each machine instruction.

For example, the architecture shown to the right employs a register file with two read ports, which allows the values stored in any two registers (or the same register) to be ALU operands. Alternatively, it allows either ALU operand to be sourced from an immediate operand (a constant value which is directly encoded in the machine instruction) or from memory. The ALU result may be written to any register in the register file (via the register file's write port) or to memory.

Multiple-precision arithmetic

In integer arithmetic computations, multiple-precision arithmetic is an algorithm that operates on integers which are larger than the ALU word size. To do this, the algorithm treats each integer as an ordered collection of ALU-size fragments, arranged from most-significant (MS) to least-significant (LS) or vice versa. For example, in the case of an 8-bit ALU, the 24-bit integer 0x123456 would be treated as a collection of three 8-bit fragments: 0x12 (MS), 0x34, and 0x56 (LS). Since the size of a fragment exactly matches the ALU word size, the ALU can directly operate on this "piece" of operand.

The algorithm uses the ALU to directly operate on particular operand fragments and thus generate a corresponding fragment (a "partial") of the multi-precision result. Each partial, when generated, is written to an associated region of storage that has been designated for the multiple-precision result. This process is repeated for all operand fragments so as to generate a complete collection of partials, which is the result of the multiple-precision operation.

In arithmetic operations (e.g., addition, subtraction), the algorithm starts by invoking an ALU operation on the operands' LS fragments, thereby producing both a LS partial and a carry out bit. The algorithm writes the partial to designated storage, whereas the processor's state machine typically stores the carry out bit to an ALU status register. The algorithm then advances to the next fragment of each operand's collection and invokes an ALU operation on these fragments along with the stored carry bit from the previous ALU operation, thus producing another (more significant) partial and a carry out bit. As before, the carry bit is stored to the status register and the partial is written to designated storage. This process repeats until all operand fragments have been processed, resulting in a complete collection of partials in storage, which comprise the multi-precision arithmetic result.

In multiple-precision shift operations, the order of operand fragment processing depends on the shift direction. In left-shift operations, fragments are processed LS first because the LS bit of each partial—which is conveyed via the stored carry bit—must be obtained from the MS bit of the previously left-shifted, less-significant operand. Conversely, operands are processed MS first in right-shift operations because the MS bit of each partial must be obtained from the LS bit of the previously right-shifted, more-significant operand.

In bitwise logical operations (e.g., logical AND, logical OR), the operand fragments may be processed in any arbitrary order because each partial depends only on the corresponding operand fragments (the stored carry bit from the previous ALU operation is ignored).

Binary fixed-point addition and subtraction

Binary fixed-point values are represented by integers. Consequently, for any particular fixed-point scale factor (or implied radix point position), an ALU can directly add or subtract two fixed-point operands and produce a fixed-point result. This capability is commonly used in both fixed-point and floating-point addition and subtraction.

In floating-point addition and subtraction, the significand of the smaller operand is right-shifted so that its fixed-point scale factor matches that of the larger operand. The ALU then adds or subtracts the aligned significands to produce a result significand. Together with other operand elements, the result significand is normalized and rounded to produce the floating-point result.

Complex operations

Although it is possible to design ALUs that can perform complex functions, this is usually impractical due to the resulting increases in circuit complexity, power consumption, propagation delay, cost and size. Consequently, ALUs are typically limited to simple functions that can be executed at very high speeds (i.e., very short propagation delays), with more complex functions being the responsibility of software or external circuitry. For example:

In simple cases in which a CPU contains a single ALU, the CPU typically implements a complex operation by orchestrating a sequence of ALU operations according to a software algorithm.
More specialized architectures may use multiple ALUs to accelerate complex operations. In such systems, the ALUs are often pipelined, with intermediate results passing through ALUs arranged like a factory production line. Performance is greatly improved over that of a single ALU because all of the ALUs operate concurrently and software overhead is significantly reduced.

Graphics processing units

Graphics processing units (GPUs) often contain hundreds or thousands of ALUs which can operate concurrently. Depending on the application and GPU architecture, the ALUs may be used to simultaneously process unrelated data or to operate in parallel on related data. An example of the latter is graphics rendering, in which multiple ALUs perform the same operation in parallel on a group of pixels, with each ALU operating on a pixel within a scene.

Implementation

An ALU is usually implemented either as a stand-alone integrated circuit (IC), such as the 74181, or as part of a more complex IC. In the latter case, an ALU is typically instantiated by synthesizing it from a description written in VHDL, Verilog or some other hardware description language. For example, the following VHDL code describes a very simple 8-bit ALU:

<span id="mwARY"></span><span class="k" id="mwARc">entity</span><span class="w" id="mwARg"> </span><span class="nc" id="mwARk">alu</span><span class="w" id="mwARo"> </span><span class="k" id="mwARs">is</span> <span class="k" id="mwARw">port</span><span class="w" id="mwAR0"> </span><span class="p" id="mwAR4">(</span><span class="w" id="mwAR8"> </span><span class="c1" id="mwASA">-- the alu connections to external circuitry:</span> <span class="w" id="mwASE"> </span><span class="n" id="mwASI">A</span><span class="w" id="mwASM"> </span><span class="o" id="mwASQ">:</span><span class="w" id="mwASU"> </span><span class="k" id="mwASY">in</span><span class="w" id="mwASc"> </span><span class="kt" id="mwASg">signed</span><span class="p" id="mwASk">(</span><span class="mi" id="mwASo">7</span><span class="w" id="mwASs"> </span><span class="k" id="mwASw">downto</span><span class="w" id="mwAS0"> </span><span class="mi" id="mwAS4">0</span><span class="p" id="mwAS8">);</span><span class="w" id="mwATA"> </span><span class="c1" id="mwATE">-- operand A</span> <span class="w" id="mwATI"> </span><span class="n" id="mwATM">B</span><span class="w" id="mwATQ"> </span><span class="o" id="mwATU">:</span><span class="w" id="mwATY"> </span><span class="k" id="mwATc">in</span><span class="w" id="mwATg"> </span><span class="kt" id="mwATk">signed</span><span class="p" id="mwATo">(</span><span class="mi" id="mwATs">7</span><span class="w" id="mwATw"> </span><span class="k" id="mwAT0">downto</span><span class="w" id="mwAT4"> </span><span class="mi" id="mwAT8">0</span><span class="p" id="mwAUA">);</span><span class="w" id="mwAUE"> </span><span class="c1" id="mwAUI">-- operand B</span> <span class="w" id="mwAUM"> </span><span class="n" id="mwAUQ">OP</span><span class="w" id="mwAUU"> </span><span class="o" id="mwAUY">:</span><span class="w" id="mwAUc"> </span><span class="k" id="mwAUg">in</span><span class="w" id="mwAUk"> </span><span class="kt" id="mwAUo">unsigned</span><span class="p" id="mwAUs">(</span><span class="mi" id="mwAUw">2</span><span class="w" id="mwAU0"> </span><span class="k" id="mwAU4">downto</span><span class="w" id="mwAU8"> </span><span class="mi" id="mwAVA">0</span><span class="p" id="mwAVE">);</span><span class="w" id="mwAVI"> </span><span class="c1" id="mwAVM">-- opcode</span> <span class="w" id="mwAVQ"> </span><span class="n" id="mwAVU">Y</span><span class="w" id="mwAVY"> </span><span class="o" id="mwAVc">:</span><span class="w" id="mwAVg"> </span><span class="k" id="mwAVk">out</span><span class="w" id="mwAVo"> </span><span class="kt" id="mwAVs">signed</span><span class="p" id="mwAVw">(</span><span class="mi" id="mwAV0">7</span><span class="w" id="mwAV4"> </span><span class="k" id="mwAV8">downto</span><span class="w" id="mwAWA"> </span><span class="mi" id="mwAWE">0</span><span class="p" id="mwAWI">));</span><span class="w" id="mwAWM"> </span><span class="c1" id="mwAWQ">-- operation result</span> <span class="k" id="mwAWU">end</span><span class="w" id="mwAWY"> </span><span class="nc" id="mwAWc">alu</span><span class="p" id="mwAWg">;</span> <span class="k" id="mwAWk">architecture</span><span class="w" id="mwAWo"> </span><span class="nc" id="mwAWs">behavioral</span><span class="w" id="mwAWw"> </span><span class="k" id="mwAW0">of</span><span class="w" id="mwAW4"> </span><span class="nc" id="mwAW8">alu</span><span class="w" id="mwAXA"> </span><span class="k" id="mwAXE">is</span> <span class="k" id="mwAXI">begin</span> <span class="w" id="mwAXM"> </span><span class="k" id="mwAXQ">case</span><span class="w" id="mwAXU"> </span><span class="n" id="mwAXY">OP</span><span class="w" id="mwAXc"> </span><span class="k" id="mwAXg">is</span><span class="w" id="mwAXk"> </span><span class="c1" id="mwAXo">-- decode the opcode and perform the operation:</span> <span class="w" id="mwAXs"> </span><span class="k" id="mwAXw">when</span><span class="w" id="mwAX0"> </span><span class="s" id="mwAX4">"000"</span><span class="w" id="mwAX8"> </span><span class="o" id="mwAYA">=></span><span class="w" id="mwAYE"> </span><span class="n" id="mwAYI">Y</span><span class="w" id="mwAYM"> </span><span class="o" id="mwAYQ"><=</span><span class="w" id="mwAYU"> </span><span class="n" id="mwAYY">A</span><span class="w" id="mwAYc"> </span><span class="o" id="mwAYg">+</span><span class="w" id="mwAYk"> </span><span class="n" id="mwAYo">B</span><span class="p" id="mwAYs">;</span><span class="w" id="mwAYw"> </span><span class="c1" id="mwAY0">-- add</span> <span class="w" id="mwAY4"> </span><span class="k" id="mwAY8">when</span><span class="w" id="mwAZA"> </span><span class="s" id="mwAZE">"001"</span><span class="w" id="mwAZI"> </span><span class="o" id="mwAZM">=></span><span class="w" id="mwAZQ"> </span><span class="n" id="mwAZU">Y</span><span class="w" id="mwAZY"> </span><span class="o" id="mwAZc"><=</span><span class="w" id="mwAZg"> </span><span class="n" id="mwAZk">A</span><span class="w" id="mwAZo"> </span><span class="o" id="mwAZs">-</span><span class="w" id="mwAZw"> </span><span class="n" id="mwAZ0">B</span><span class="p" id="mwAZ4">;</span><span class="w" id="mwAZ8"> </span><span class="c1" id="mwAaA">-- subtract</span> <span class="w" id="mwAaE"> </span><span class="k" id="mwAaI">when</span><span class="w" id="mwAaM"> </span><span class="s" id="mwAaQ">"010"</span><span class="w" id="mwAaU"> </span><span class="o" id="mwAaY">=></span><span class="w" id="mwAac"> </span><span class="n" id="mwAag">Y</span><span class="w" id="mwAak"> </span><span class="o" id="mwAao"><=</span><span class="w" id="mwAas"> </span><span class="n" id="mwAaw">A</span><span class="w" id="mwAa0"> </span><span class="o" id="mwAa4">-</span><span class="w" id="mwAa8"> </span><span class="mi" id="mwAbA">1</span><span class="p" id="mwAbE">;</span><span class="w" id="mwAbI"> </span><span class="c1" id="mwAbM">-- decrement</span> <span class="w" id="mwAbQ"> </span><span class="k" id="mwAbU">when</span><span class="w" id="mwAbY"> </span><span class="s" id="mwAbc">"011"</span><span class="w" id="mwAbg"> </span><span class="o" id="mwAbk">=></span><span class="w" id="mwAbo"> </span><span class="n" id="mwAbs">Y</span><span class="w" id="mwAbw"> </span><span class="o" id="mwAb0"><=</span><span class="w" id="mwAb4"> </span><span class="n" id="mwAb8">A</span><span class="w" id="mwAcA"> </span><span class="o" id="mwAcE">+</span><span class="w" id="mwAcI"> </span><span class="mi" id="mwAcM">1</span><span class="p" id="mwAcQ">;</span><span class="w" id="mwAcU"> </span><span class="c1" id="mwAcY">-- increment</span> <span class="w" id="mwAcc"> </span><span class="k" id="mwAcg">when</span><span class="w" id="mwAck"> </span><span class="s" id="mwAco">"100"</span><span class="w" id="mwAcs"> </span><span class="o" id="mwAcw">=></span><span class="w" id="mwAc0"> </span><span class="n" id="mwAc4">Y</span><span class="w" id="mwAc8"> </span><span class="o" id="mwAdA"><=</span><span class="w" id="mwAdE"> </span><span class="k" id="mwAdI">not</span><span class="w" id="mwAdM"> </span><span class="n" id="mwAdQ">A</span><span class="p" id="mwAdU">;</span><span class="w" id="mwAdY"> </span><span class="c1" id="mwAdc">-- 1's complement</span> <span class="w" id="mwAdg"> </span><span class="k" id="mwAdk">when</span><span class="w" id="mwAdo"> </span><span class="s" id="mwAds">"101"</span><span class="w" id="mwAdw"> </span><span class="o" id="mwAd0">=></span><span class="w" id="mwAd4"> </span><span class="n" id="mwAd8">Y</span><span class="w" id="mwAeA"> </span><span class="o" id="mwAeE"><=</span><span class="w" id="mwAeI"> </span><span class="n" id="mwAeM">A</span><span class="w" id="mwAeQ"> </span><span class="k" id="mwAeU">and</span><span class="w" id="mwAeY"> </span><span class="n" id="mwAec">B</span><span class="p" id="mwAeg">;</span><span class="w" id="mwAek"> </span><span class="c1" id="mwAeo">-- bitwise AND</span> <span class="w" id="mwAes"> </span><span class="k" id="mwAew">when</span><span class="w" id="mwAe0"> </span><span class="s" id="mwAe4">"110"</span><span class="w" id="mwAe8"> </span><span class="o" id="mwAfA">=></span><span class="w" id="mwAfE"> </span><span class="n" id="mwAfI">Y</span><span class="w" id="mwAfM"> </span><span class="o" id="mwAfQ"><=</span><span class="w" id="mwAfU"> </span><span class="n" id="mwAfY">A</span><span class="w" id="mwAfc"> </span><span class="k" id="mwAfg">or</span><span class="w" id="mwAfk"> </span><span class="n" id="mwAfo">B</span><span class="p" id="mwAfs">;</span><span class="w" id="mwAfw"> </span><span class="c1" id="mwAf0">-- bitwise OR</span> <span class="w" id="mwAf4"> </span><span class="k" id="mwAf8">when</span><span class="w" id="mwAgA"> </span><span class="s" id="mwAgE">"111"</span><span class="w" id="mwAgI"> </span><span class="o" id="mwAgM">=></span><span class="w" id="mwAgQ"> </span><span class="n" id="mwAgU">Y</span><span class="w" id="mwAgY"> </span><span class="o" id="mwAgc"><=</span><span class="w" id="mwAgg"> </span><span class="n" id="mwAgk">A</span><span class="w" id="mwAgo"> </span><span class="k" id="mwAgs">xor</span><span class="w" id="mwAgw"> </span><span class="n" id="mwAg0">B</span><span class="p" id="mwAg4">;</span><span class="w" id="mwAg8"> </span><span class="c1" id="mwAhA">-- bitwise XOR</span> <span class="w" id="mwAhE"> </span><span class="k" id="mwAhI">when</span><span class="w" id="mwAhM"> </span><span class="k" id="mwAhQ">others</span><span class="w" id="mwAhU"> </span><span class="o" id="mwAhY">=></span><span class="w" id="mwAhc"> </span><span class="n" id="mwAhg">Y</span><span class="w" id="mwAhk"> </span><span class="o" id="mwAho"><=</span><span class="w" id="mwAhs"> </span><span class="p" id="mwAhw">(</span><span class="k" id="mwAh0">others</span><span class="w" id="mwAh4"> </span><span class="o" id="mwAh8">=></span><span class="w" id="mwAiA"> </span><span class="sc" id="mwAiE">'X'</span><span class="p" id="mwAiI">);</span> <span class="w" id="mwAiM"> </span><span class="k" id="mwAiQ">end</span><span class="w" id="mwAiU"> </span><span class="k" id="mwAiY">case</span><span class="p" id="mwAic">;</span> <span class="k" id="mwAig">end</span><span class="w" id="mwAik"> </span><span class="nc" id="mwAio">behavioral</span><span class="p" id="mwAis">;</span>

History

Mathematician John von Neumann proposed the ALU concept in 1945 in a report on the foundations for a new computer called the EDVAC.

The cost, size, and power consumption of electronic circuitry was relatively high throughout the infancy of the Information Age. Consequently, all early computers had a serial ALU that operated on one data bit at a time although they often presented a wider word size to programmers. The first computer to have multiple parallel discrete single-bit ALU circuits was the 1951 Whirlwind I, which employed sixteen such "math units" to enable it to operate on 16-bit words.

In 1967, Fairchild introduced the first ALU-like device implemented as an integrated circuit, the Fairchild 3800, consisting of an eight-bit arithmetic unit with accumulator. It only supported adds and subtracts but no logic functions.

Full integrated-circuit ALUs soon emerged, including four-bit ALUs such as the Am2901 and 74181. These devices were typically "bit slice" capable, meaning they had "carry look ahead" signals that facilitated the use of multiple interconnected ALU chips to create an ALU with a wider word size. These devices quickly became popular and were widely used in bit-slice minicomputers.

Microprocessors began to appear in the early 1970s. Even though transistors had become smaller, there was sometimes insufficient die space for a full-word-width ALU and, as a result, some early microprocessors employed a narrow ALU that required multiple cycles per machine language instruction. Examples of this include the popular Zilog Z80, which performed eight-bit additions with a four-bit ALU. Over time, transistor geometries shrank further, following Moore's law, and it became feasible to build wider ALUs on microprocessors.

Modern integrated circuit (IC) transistors are orders of magnitude smaller than those of the early microprocessors, making it possible to fit highly complex ALUs on ICs. Today, many modern ALUs have wide word widths, and architectural enhancements such as barrel shifters and binary multipliers that allow them to perform, in a single clock cycle, operations that would have required multiple operations on earlier ALUs.

ALUs can be realized as mechanical, electro-mechanical or electronic circuits and, in recent years, research into biological ALUs has been carried out (e.g., actin-based).