CLMUL instruction set
- 1 min read
- 2 chapters
Related on Lably
Through Microprocessor
One use of these instructions is to improve the speed of applications doing block cipher encryption in Galois/Counter Mode, which depends on finite field GF(2k) multiplication. Another application is the fast calculation of CRC values, including those used to implement the LZ77 sliding window DEFLATE algorithm in zlib and pngcrush.
ARMv8 also has a version of CLMUL. SPARC calls their version XMULX, for "XOR multiplication".
New instructions
The instruction computes the 128-bit carry-less product of two 64-bit values. The destination is a 128-bit XMM register. The source may be another XMM register or memory. An immediate operand specifies which halves of the 128-bit operands are multiplied. Mnemonics specifying specific values of the immediate operand are also defined:
A EVEX vectorized version (VPCLMULQDQ) is seen in AVX-512.
Sign in to keep reading
One more chapter is free with a Lably account.
CPUs with CLMUL instruction set
- Intel
- AMD:
- Jaguar-based processors and newer
- Puma-based processors and newer
- "Heavy Equipment" processors
- Bulldozer-based processors
- Piledriver-based processors
- Steamroller-based processors
- Excavator-based processors and newer
- Zen processors
- Zen+ processors
- Zen2 (and later) processors
The presence of the CLMUL instruction set can be checked by testing one of the CPU feature bits.

