GE 645

Architecture

Processor Modes

The GE-645 has two modes of Instruction Execution (Master and Slave) inherited from the GE-635, however it also adds another dimension by having two modes of memory addressing (Absolute and Appending). When the process is executing in Absolute Mode addressing is limited to 2¹⁸ words of memory and any instructions are executed in Master mode. In comparison Append Mode calculates the address using "Appending Words" with an address space of 2²⁴ words and with instruction execution occurring in either Master or Slave modes.

Slave Mode

By default this is normal mode that the processor should be executing in at any point in time. Nearly all instructions will run in this mode aside from a small set of privileged instructions which cannot execute in this mode. Execution of such instructions will trigger an illegal procedure fault, also the ability to inhibit interrupts (bit 28 of instruction word) is forbidden. Format of instruction addresses is via the Appending Process.

Master Mode

In this mode the processor can execute all instructions and is able to inhibit interrupts while doing so. Like in Slave mode the default form of address formation is via the Appending Process.

Absolute Mode

All instructions can be executed in this mode and full access is given to any privileged features of the hardware. Interrupts can be inhibited and instruction fetching is limited to a 2¹⁸ (18-bit) absolute address thus restricting the processor to only been able to access the lower 256 KW of physical core memory. The processor will switch to this mode in the event of a fault or interrupt and will remain in it until it executes transfer instruction whose operand address has been obtained via the appending process.

Appending Mode

By default this is normal mode of Memory addressing, both Master and Slave modes normally operate in this mode. Indirect words and operands are accessed via Appending Mechanism via the process of placing a 1 in bit 29 of the executed instruction. Effective addresses are thus either added to a base address, or the offset is linked to the base address.

Functional Units

The 645 processor was divided into four major functional units these were:

• Appending Unit:
  • Controls data I/O from memory
  • Controls memory selection and interleave
  • Carries out Memory appending
  • Control fault recognition
  • Does power on/off sequencing
• Associative Memory Unit:
  • Consists of Associative Memory made up of 16 x 60-bit Registers
  • Registers point to most recently used segment (Segment Descriptor Word) or most recently used Page (Page Table)
  • Performs the function of what would now be classed as a TLB.
• Control Unit:
  • Performs all control functions
  • Performs Address modification
  • Controls the processor mode (master, slave, absolute)
  • Interrupt recognition/handling
  • Opcode decoding
• Operations Unit:
  • Performs fractional and integer divisions and multiplications.
  • Performs automatic alignment of floating-point numbers for addition and subtraction.
  • Performs inverted divisions on floating-point numbers.
  • Performs automatic normalization of floating-point resultants.
  • Performs shifts.
  • Performs indicator register loading and storing.
  • Performs timer register loading and decrementing.

One of the key differences from the GE 635 was the addition of "appending unit" (APU) which was used to implement a hybrid "Paged Segmentation" model of virtual memory. The APU was also used to implement a single-level store which is one of the fundamental abstraction that Multics is built around. The instruction format was also extended with the previously unused bit 29 controlling whether the operand address of an instruction used an 18-bit format (bit 29 = 0) or one that was made up of a 3-bit Base Register address with a 15-bit offset (bit 29 = 1).

The instruction format with bit 29 set to 1 is:

1 1 2 2 2 2 3 3 0 2 3 7 8 6 7 8 9 0 5 +---+---------------+---------+-+-+-+------+ |BR | Y | OP |0|I|1| Tag | +---+---------------+---------+-+-+-+------+

• B is the base register field
• Y is the address field (15 bits), addressing 32KW
• OP is the opcode (9 bits), the additional bit 27 is the opcode extension bit.
• I is the interrupt inhibit bit.
• Tag indicates the type of address modification to be performed; some additional tags are supported by the GE 645.

Address base registers

The GE 645 had 8 Address Base Registers (abr's), these could operate in either "paired" or "unpaired" modes. The later Honeywell 6180 changed these to 8 pointer registers. Each abr was 24-bits wide consisting of 18 bits for an address and 6 bits for control functions.

One bit of the control functions field indicates where an abr is "internal" or "external". If an abr is internal, another 3-bit subfield of the control functions field specifies another abr with which this abr is paired; that other abr is external, with the external abr containing a segment number in the address field and the internal abr containing an offset within the segment specified by the external abr. If an instruction or an indirect word refers to an external abr, the address field in the instruction or indirect word is used as an offset in the segment specified by the external abr. If it refers to an internal abr, the address field in the instruction or indirect word is added to the offset in the abr, and the resulting value is used as an offset in the segment specified by the external abr with which the internal abr is paired.

The registers have the following formats depending on how bit 21 is set.

Format as an "external" base, with bit 21 set:

1 1 2 2 22 0 7 8 0 1 23 +------------------+---+-+--+ | PDW |\\\|1|\\| +------------------+---+-+--+

Format as a component to the effective "internal" address with a pointer to an "external" base, with bit 21 clear:

1 1 2 2 22 0 7 8 0 1 23 +------------------+---+-+--+ | PY |PB |0|\\| +------------------+---+-+--+

• PDW is the Pointer to a descriptor word
• PY is the component P of the effective internal address 'Y'
• PB is pointer to another base register whose bit 21 = 1

In Multics, an even-numbered abr and the following odd-numbered abr were paired. When writing in Assembly (EPLBSA/ALM) the standard Multics practice was to label these registers as follows:

• ap for abr 0
• ab for abr 1
• bp for abr 2
• bb for abr 3
• lp for abr 4
• lb for abr 5
• sp for abr 6
• sb for abr 7

The naming scheme is based around the following:

• a for argument-list pointer
• b for general base
• l for linkage-segment pointer
• s for stack-segment pointer

The 8 pointer registers in the Honeywell 6180 and its successors served the same purpose as the 4 paired base registers in the GE-645, referring to an offset within a segment.

History

CTSS had originated in the MIT Computation Center using a IBM 709 and was first demonstrated in November 1961, it was subsequently upgraded to a 7090 in 1962, and finally to a 7094 in 1963. This required modification to these standard systems via the addition of a number of RPQ's which among others added two banks of memory and bank-switching between user and supervisor mode, i.e. programs running in the A-core memory bank had access to instructions that programs running in the B-core bank did not.

Project MAC formally began with signing of contract with ARPA on the 1st of July 1963. By October 1963 they had received a dedicated 7094 to run CTSS under, this was termed the "Red Machine" due to it having red side panels. This would provide a time-sharing environment for Project MAC, and would subsequently be heavily used for the development of Multics. During this period exploratory work was carried out into what a replacement for CTSS would look like and what type of hardware it would require to run on. A committee was formed consisting of Fernando J. Corbató, Ted Glaser, Jack Dennis and Robert Graham with responsibility to visit computer manufacturers to gauge level of interest in the industry to tender for the hardware platform. It was made clear that Project MAC was looking for a development partner given the considerable hardware modifications that would be required to meet their requirements, which were specified as:

1. User Programs having read/write protection.
2. That privileged instructions would not be accessible to end user programs
3. At least the ability to address 256KW of memory directly.
4. Native multiprocessing capability with all processors been of equivalent functional level
5. Effective support for telecommunications which could handle both conventional telephone lines as well as high speed data links that could run graphic display terminals such as the MIT-developed Kludge graphical terminal.
6. Mass storage units, including a fast drum that could be used as a paging device.
7. Hardware support for both segmentation and paging with support for a content addressable memory (CAM) so as to reduce virtual memory overhead.

They proceeded to visit among others Burroughs, CDC, DEC, General Electric, IBM and Sperry Univac. Of these GE and IBM showed the strongest interest. By the summer of 1964 proposals was received from DEC, IBM and GE, after evaluations by the Technical Committee a unanimous decision was made to accept the GE proposal for the GE 645 which was a design based on the GE 635 but modified to meet the requirements outlined above.

While the GE 645 hardware was being designed and debugged in Phoenix, a system was put in place where a GE 635 could be used to run a simulator known as the 6.36, so that development and checkout of Multics could occur in parallel. This process involved creating a tape on the CTSS system which would be inputted to GECOS on the 635 system in MIT so that it would run under the 6.36 simulator; the resulting output would be carried back via tape to CTSS for debugging/analysis. This simulated environment was replaced by the first 645 hardware in 1967. The GECOS operating system was fully replaced by Multics in 1969 with the Multics supervisor separated by protection rings with "gates" allowing access from user mode.

A later generation in the form of the 645F (F for follow-on) wasn't completed by the time the division was sold to Honeywell, and became known as the Honeywell 6180. The original access control mechanism of the GE/Honeywell 645 were found inadequate for high speed trapping of access instructions and the re-implementation in the 6180 solved those problems. The bulk of these computers running time-sharing on Multics were installed at the NSA and similar governmental sites. Their usage was limited by the extreme security measures and had limited impact on subsequent systems, other than the protection ring.

The hardware protection introduced on this computer and modified on the 6180 was later implemented in the Intel 286 computer processor as a four-layer protection ring, but four rings was found to be too cumbersome to program and too slow to operate. Protection ring architecture is now used only to protect kernel mode from user mode code just as it was in the original use of the 645.