Gracemont (microarchitecture)
CPU microarchitecture by Intel
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Design
Gracemont is the fourth generation out-of-order low-power Atom microarchitecture, built on the Intel 7 manufacturing process.
The Gracemont microarchitecture has the following enhancements over Tremont:
- Level 1 cache per core:
- Eight-way-associative 64 KB instruction cache
- Eight-way-associative 32 KB data cache
- New on-demand instruction-length decoder
- Instruction issue increased to five per clock (from four)
- Instruction retire increased to eight per clock (from seven)
- Execution ports (functional units) there are now 17 (from ten)
- Reorder buffer increased to 256 entries (from 208)
- Improved branch prediction
- Support for AVX, AVX2, FMA3 and AVX-VNNI instructions
- 2 or 4 MB shared L2 cache per 4-core cluster. Alder Lake family has 2 MB. Higher-end Raptor Lake family with Raptor Cove has 4 MB, while Lower-end Raptor Lake family with Golden Cove has 2 MB.
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Technology
- System on a chip (SoC) architecture
- 3D tri-gate transistors
- Thermal design power (TDP)
- 10 W desktop processors
- 6 W mobile processors
List of Gracemont processors
The microarchitecture is used as the efficient cores of the 12th generation of Intel Core hybrid processors (codenamed "Alder Lake"), the 13th generation of Intel Core hybrid processors (codenamed "Raptor Lake") and the 14th generation of Intel Core hybrid processors (codenamed "Raptor Lake Refresh"). It's also used in the Alder Lake-N line-up as the only core cluster, intended for low-power applications.