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Nanoelectromechanical systems

Class of devices for nanoscale functionality

  • 15 min read
  • 8 chapters
The SiTime SiT8008 is a programmable MEMS oscillator reaching quartz precision but with higher reliability and lower g-sensitivity. MEMS die size 457x454µm. Total die size 1409x1572µm. Poly level.
ZeptoBars · CC BY 3.0

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History

Background

As noted by Richard Feynman in his famous talk in 1959, "There's Plenty of Room at the Bottom", there are many potential applications of machines at smaller and smaller sizes; by building and controlling devices at smaller scales, all technology benefits. The expected benefits include greater efficiencies and reduced size, decreased power consumption and lower costs of production in electromechanical systems.

The first silicon dioxide field effect transistors were built by Frosch and Derick in 1957 at Bell Labs. In 1960, Atalla and Kahng at Bell Labs fabricated a MOSFET with a gate oxide thickness of 100 nm. In 1962, Atalla and Kahng fabricated a nanolayer-base metal–semiconductor junction (M–S junction) transistor that used gold (Au) thin films with a thickness of 10 nm. In 1987, Bijan Davari led an IBM research team that demonstrated the first MOSFET with a 10 nm oxide thickness. Multi-gate MOSFETs enabled scaling below 20 nm channel length, starting with the FinFET. The FinFET originates from the research of Digh Hisamoto at Hitachi Central Research Laboratory in 1989. At UC Berkeley, a group led by Hisamoto and TSMC's Chenming Hu fabricated FinFET devices down to 17 nm channel length in 1998.

NEMS

In 2000, the first very-large-scale integration (VLSI) NEMS device was demonstrated by researchers at IBM. Its premise was an array of AFM tips which can heat/sense a deformable substrate in order to function as a memory device (Millipede memory). Further devices have been described by Stefan de Haan. In 2007, the International Technical Roadmap for Semiconductors (ITRS) contains NEMS memory as a new entry for the Emerging Research Devices section.

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