POWER4

Functional layout

The POWER4 has a unified L2 cache, divided into three equal parts. Each has its own independent L2 controller which can feed 32 bytes of data per cycle. The Core Interface Unit (CIU) connects each L2 controller to either the data cache or instruction cache in either of the two processors. The Non-Cacheable (NC) Unit is responsible for handling instruction serializing functions and performing any noncacheable operations in the storage topology. There is an L3 cache controller, but the actual memory is off-chip. The GX bus controller controls I/O device communications, and there are two 4-byte wide GX buses, one incoming and the other outgoing. The Fabric Controller is the master controller for the network of buses, controlling communications for both L1/L2 controllers, communications between POWER4 chips {4-way, 8-way, 16-way, 32-way} and POWER4 MCM's. Trace-and-Debug, used for First Failure Data Capture, is provided. There is also a Built In Self Test function (BIST) and Performance Monitoring Unit (PMU). Power-on reset (POR) is supported.

Execution units

The POWER4 implements a superscalar microarchitecture through high-frequency speculative out-of-order execution using eight independent execution units. They are: two floating-point units (FP1-2), two load-store units (LD1-2), two fixed-point units (FX1-2), a branch unit (BR), and a conditional-register unit (CR). These execution units can complete up to eight operations per clock (not including the BR and CR units):

• each floating point unit can complete one fused multiply–add per clock (two operations),
• each load–store unit can complete one instruction per clock,
• each fixed-point unit can complete one instruction per clock.

The pipeline stages are:

• Branch Prediction
• Instruction Fetch
• Decode, Crack and Group Formation
• Group Dispatch and Instruction Issue
• Load–Store Unit Operation
  • Load Hit Store
  • Store Hit Load
  • Load Hit Load
• Instruction Execution Pipeline