PowerPC e6500

Design

It has a revised memory subsystem compared to the previous e5500 core with four cores combined into a CPU Cluster, sharing a large L2 cache and the e6500 cores supports up to eight CPU Clusters for very large multiprocessing implementations. The core is the first multithreaded core designed by Freescale and reintroduces an enhanced version of AltiVec to their products. The multithreading allows for two virtual cores per hard core and is organized as 2x2-way superscalar. One virtual core in an e6500 can often perform better than an entire e5500 core since Freescale essentially duplicated a lot of logic instead of just virtualizing it, in addition to other enhancements to the core.

Each core has five integer units (four simple and one complex), two load-store units, one 128-bit AltiVec unit, 32+32 kB instruction and data L1 caches. Speeds range up to 2.5 GHz, and the core is designed to be highly configurable via the CoreNet fabric and meet the specific needs of embedded applications with features like multi-core operation and interface for auxiliary application processing units (APU).

e6501

The e6501 core is a revision introduced in 2013 with enhanced virtualization interrupt support.