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Subtractor

Circuit that performs subtraction

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Through Electronics, Adder (electronics) and Binary number

Di=X⊕Yi⊕Bi
Bi+1=Xi<(Yi+Bi),

where ⊕ represents exclusive or.

Subtractors are usually implemented within a binary adder for only a small cost when using the standard two's complement notation, by providing an addition/subtraction selector to the carry-in and to invert the second operand.

−B=B¯+1 (definition of two's complement notation)
A−B=A+(−B)=A+B¯+1

Half subtractor

The half subtractors can be designed through the combinational Boolean logic circuits [2] as shown in Figure 1 and 2. The half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, the minuend X and subtrahend Y and two outputs the difference D and borrow out Bout. The borrow out signal is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That is, Bout=1 when X<Y. Since X and Y are bits, Bout=1 if and only if X=0 and Y=1. An important point worth mentioning is that the half subtractor diagram aside implements X−Y and not Y−X since Bout on the diagram is given by

Bout=X¯⋅Y.

This is an important distinction to make since subtraction itself is not commutative, but the difference bit D is calculated using an XOR gate which is commutative.

The truth table for the half subtractor is:

Using the table above and a Karnaugh map, we find the following logic equations for D and Bout:

D=X⊕Y
Bout=X¯⋅Y.

Consequently, a simplified half-subtract circuit, advantageously avoiding crossed traces in particular as well as a negate gate is:

X ── XOR ─┬─────── |X-Y|, is 0 if X equals Y, 1 otherwise ┌──┘ └──┐ Y ─┴─────── AND ── borrow, is 1 if Y > X, 0 otherwise

where lines to the right are outputs and others (from the top, bottom or left) are inputs.

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