ARM Cortex-A17

ARM renamed Cortex-A12 to a variant of Cortex-A17 since the second revision of the A12 core in early 2014, because these two were indistinguishable in performance and all features available in the A17 were used as upgrades in the A12.

New features of the Cortex-A17 specification, not found in the Cortex-A9 specification, are all improvements from the third-generation ARM Cortex-A, which also includes the Cortex-A7 and Cortex-A15:

• Hardware virtualization and 40-bit Large Physical Address Extensions (LPAE) addressing
• Full-system coherency, bringing support for the big.LITTLE architecture
• NEON unit, for floating-point data and SIMD processing
• Deeper integer instruction pipeline, with 10–12 stages
• Full out-of-order execution design with load/store units

Modern Linux kernel implementations will report and support the above features thus :

processor : 3 model name : ARMv7 Processor rev 1 (v7l) BogoMIPS : 48.00 Features : <span about="#mwt48" typeof="mw:Transclusion" data-mw='{"parts":[{"template":{"target":{"wt":"not a typo","href":"./Template:Not_a_typo"},"params":{"1":{"wt":"half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm"}},"i":0}}]}' id="mwNg">half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm</span> CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0 CPU part : 0xc0d CPU revision : 1