ARM big.LITTLE
Heterogeneous computing architecture
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In October 2011, big.LITTLE was announced along with the Cortex-A7, which was designed to be architecturally compatible with the Cortex-A15. In October 2012, ARM announced the Cortex-A53 and Cortex-A57 (ARMv8-A) cores, which are also intercompatible to allow their use in a big.LITTLE chip. ARM later announced the Cortex-A12 at Computex 2013 followed by the Cortex-A17 in February 2014. Both the Cortex-A12 and the Cortex-A17 can also be paired in a big.LITTLE configuration with the Cortex-A7.
Advantages
For a given library of CMOS logic, active power increases as the logic switches more per second, while leakage increases with the number of transistors. When a very fast out-of-order CPU is idling at very low speeds, a CPU with much less leakage (fewer transistors) could do the same work. For example, it might use a smaller memory cache, or a simpler microarchitecture such as removing out-of-order execution. big.LITTLE is a way to optimize for both power efficiency and speed in the same system.
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Disadvantages
In practice, a big.LITTLE system can be surprisingly inflexible. One issue is the number and types of power and clock domains that the SoC provides, which may not match the standard power management features offered by an operating system. Another is that the CPUs no longer have equivalent abilities, and matching the right software task to the right CPU becomes more difficult. Most of these problems are being solved by making the electronics and software more flexible.
Run-state migration
There are three ways for the different processor cores to be arranged in a big.LITTLE design, depending on the actual SoC layout and the scheduler implemented in the kernel.
Clustered switching
The clustered model approach is the first and simplest implementation, arranging the processor into identically sized clusters of "big" or "LITTLE" cores. The operating system scheduler can only see one cluster at a time; when the load on the whole processor changes between low and high, the system transitions to the other cluster. All relevant data are then passed through the common L2 cache, the active core cluster is powered off and the other one is activated. A Cache Coherent Interconnect (CCI) is used. This model has been implemented in the Samsung Exynos 5 Octa (5410).
In-kernel switcher (CPU migration)
CPU migration via the in-kernel switcher (IKS) involves pairing up a "big" core with a "LITTLE" core, with possibly many identical pairs in one chip. Each pair operates as one so-termed virtual core, and only one real core is (fully) powered up and running at a time. The "big" core is used when the demand is high and the "LITTLE" core is employed when demand is low. When demand on the virtual core changes (between high and low), the incoming core is powered up, running state is transferred, the outgoing is shut down, and processing continues on the new core. Switching is done via the cpufreq framework. A complete big.LITTLE IKS implementation was added in Linux 3.11. big.LITTLE IKS is an improvement of cluster migration (§ Clustered switching), the main difference being that each pair is visible to the scheduler.
A more complex arrangement involves a non-symmetric grouping of "big" and "LITTLE" cores. A single chip could have one or two "big" cores and many more "LITTLE" cores, or vice versa. Nvidia created something similar to this with the low-power "companion core" in their Tegra 3 System-on-Chip.
Heterogeneous multi-processing (global task scheduling)
The most powerful use model of big.LITTLE architecture is heterogeneous multi-processing (HMP), which enables the use of all physical cores at the same time. Threads with high priority or computational intensity can in this case be allocated to the "big" cores while threads with less priority or less computational intensity, such as background tasks, can be performed by the "LITTLE" cores. This model also does not require matching numbers of the "big" and "LITTLE" cores.
This model has been implemented in the Samsung Exynos starting with the Exynos 5 Octa series (5420, 5422, 5430), and Apple A series processors starting with the Apple A11. Another example is the hexa-core Rockchip RK3399 SoC.
Scheduling
The paired arrangement allows for switching to be done transparently to the operating system using the existing dynamic voltage and frequency scaling (DVFS) facility. The existing DVFS support in the kernel (e.g. cpufreq in Linux) will simply see a list of frequencies/voltages and will switch between them as it sees fit, just like it does on the existing hardware. However, the low-end slots will activate the 'Little' core and the high-end slots will activate the 'Big' core. This is the early solution provided by Linux's "deadline" CPU scheduler (not to be confused with the I/O scheduler with the same name) since 2012.
Alternatively, all the cores may be exposed to the kernel scheduler, which will decide where each process/thread is executed. This will be required for the non-paired arrangement but could possibly also be used on the paired cores. It poses unique problems for the kernel scheduler, which, at least with modern commodity hardware, has been able to assume all cores in a SMP system are homogenous rather than heterogeneous. A 2019 addition to Linux 5.0 called Energy Aware Scheduling is an example of a scheduler that considers cores differently.
Advantages of global task scheduling
- Finer-grained control of workloads that are migrated between cores. Because the scheduler is directly migrating tasks between cores, kernel overhead is reduced and power savings can be correspondingly increased.
- Implementation in the scheduler also makes switching decisions faster than in the cpufreq framework implemented in IKS.
- The ability to easily support non-symmetrical clusters (e.g. with 2 Cortex-A15 cores and 4 Cortex-A7 cores).
- The ability to use all cores simultaneously to provide improved peak performance throughput of the SoC compared to IKS.
Successor
In May 2017, ARM announced DynamIQ as the successor to big.LITTLE. DynamIQ is expected to allow for more flexibility and scalability when designing multi-core processors. In contrast to big.LITTLE, it increases the maximum number of cores in a cluster to 8 for Armv8.2 CPUs, 12 for Armv9 and 14 for Armv9.2 and allows for varying core designs within a single cluster, and up to 32 total clusters. The technology also offers more fine grained per core voltage control and faster L2 cache speeds.
However, DynamIQ is incompatible with previous ARM designs and is initially only supported by the Cortex-A75 and Cortex-A55 CPU cores and their successors.