ARM Cortex-A57
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Through ARM big.LITTLE
Overview
- Pipelined processor with deeply out of order, speculative issue 3-way superscalar execution pipeline
- DSP and NEON SIMD extensions are mandatory per core
- VFPv4 Floating Point Unit onboard (per core)
- Hardware virtualization support
- Thumb-2 instruction set encoding reduces the size of 32-bit programs with little impact on performance.
- TrustZone security extensions
- Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution
- 32 KiB data (2-way set-associative) + 48 KiB instruction (3-way set-associative) L1 cache per core
- Integrated low-latency level-2 (16-way set-associative) cache controller, 512 KB, 1 MB, or 2 MB configurable size per cluster
- 48-entry fully associative L1 instruction Translation Lookaside Buffer (TLB) with native support for 4 KiB, 64 KiB, and 1 MB page sizes
- 4-way set-associative of 1024-entry L2 TLB
- 2-level dynamic predictor with Branch Target Buffer (BTB) for fast target generation
- Static branch predictor
- Indirect predictor
- Return stack
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Chips
In January 2014, AMD announced the Opteron A1100. Intended for servers, the A1100 has four or eight Cortex-A57 cores, support for up to 128 GiB of DDR3 or DDR4 RAM, an eight-lane PCIe controller, eight SATA (6 Gbit/s) ports, and two 10 Gigabit Ethernet ports. The A1100 series was released in January 2016, with four and eight core versions.
Qualcomm's first offering which was made available for sampling Q4 2014 was the Snapdragon 810. It contains four Cortex-A57 and four Cortex-A53 cores in a big.LITTLE configuration.
Samsung also provides Cortex-A57-based SoC's, the first one being Exynos Octa 5433 which was available for sampling from Q4 2014.
In March, 2015, Nvidia released the Tegra X1 SoC, which has four A57 cores running at a maximum of 2 GHz.