Capacitance–voltage profiling
Technique for characterizing semiconductor materials and devices
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Through Semiconductor, Voltage and Capacitance
Application
Many researchers use capacitance–voltage (C–V) testing to determine semiconductor parameters, particularly in MOSCAP and MOSFET structures. However, C–V measurements are also widely used to characterize other types of semiconductor devices and technologies, including bipolar junction transistors, JFETs, III–V compound devices, photovoltaic cells, MEMS devices, organic thin-film transistor (TFT) displays, photodiodes, and carbon nanotubes (CNTs).
These measurements' fundamental nature makes them applicable to a wide range of research tasks and disciplines. For example, researchers use them in university and semiconductor manufacturers' labs to evaluate new processes, materials, devices, and circuits. These measurements are extremely valuable to product and yield enhancement engineers who are responsible for improving processes and device performance. Reliability engineers also use these measurements to qualify the suppliers of the materials they use, to monitor process parameters, and to analyze failure mechanisms.
A multitude of semiconductor device and material parameters can be derived from C–V measurements with appropriate methodologies, instrumentation, and software. This information is used throughout the semiconductor production chain, and begins with evaluating epitaxially grown crystals, including parameters such as average doping concentration, doping profiles, and carrier lifetimes.
C–V measurements can reveal oxide thickness, oxide charges, contamination from mobile ions, and interface trap density in wafer processes. A C–V profile as generated on nanoHUB for bulk MOSFET with different oxide thicknesses. Notice that the red curve indicates low frequency whereas the blue curve illustrates the high-frequency C–V profile. Pay particular attention to the shift in threshold voltage with different oxide thicknesses.
These measurements continue to be important after other process steps have been performed, including lithography, etching, cleaning, dielectric and polysilicon depositions, and metallization, among others. Once devices have been fully fabricated, C–V profiling is often used to characterize threshold voltages and other parameters during reliability and basic device testing and to model device performance.
C–V measurements are done by using capacitance–voltage meters of Electronic Instrumentation. They are used to analyze the doping profiles of semiconductor devices by the obtained C–V graphs.
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C–V characteristics of metal–oxide–semiconductor structure
A metal–oxide–semiconductor structure is critical part of a MOSFET, controlling the height of potential barrier in the channel via the gate oxide.
An n-channel MOSFET's operation can be divided into three regions, shown below and corresponding to the right figure.
Depletion
When a small positive bias voltage is applied to the metal, the valence band edge is driven far from the Fermi level, and holes from the body are driven away from the gate, resulting in a low carrier density, so the capacitance is low (the valley in the middle of the figure to the right).
Inversion
At larger gate bias still, near the semiconductor surface the conduction band edge is brought close to the Fermi level, populating the surface with electrons in an inversion layer or n-channel at the interface between the semiconductor and the oxide. This results in a capacitance increase, as shown in the right part of right figure.
Accumulation
When a negative gate-source voltage (positive source-gate) is applied, it creates a p-channel at the surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and voltages. The increase in hole density corresponds to increase in capacitance, shown in the left part of right figure.