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GeForce 400 series

Series of GPUs by Nvidia

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Through Error detection and correction and Arithmetic logic unit

Its direct competitor was ATI's Radeon HD 5000 series.

Architecture

Nvidia described the Fermi microarchitecture as the next major step in its line of GPUs following the Tesla microarchitecture used since the G80. The GF100, the first Fermi-architecture product, is large: 512 stream processors, in sixteen groups of 32, and 3.0 billion transistors, manufactured by TSMC in a 40 nm process. It is Nvidia's first chip to support OpenGL 4.0 and Direct3D 11. No products with a fully enabled GF100 GPU were ever sold. The GTX 480 had one streaming multiprocessor disabled. The GTX 470 had two streaming multiprocessors and one memory controller disabled. The GTX 465 had five streaming multiprocessors and two memory controllers disabled. Consumer GeForce cards came with 256MB attached to each of the enabled GDDR5 memory controllers, for a total of 1.5, 1.25 or 1.0GB; the Tesla C2050 had 512MB on each of six controllers, and the Tesla C2070 had 1024MB per controller. Both the Tesla cards had fourteen active groups of stream processors.

The chips found in the high performance Tesla branding feature memory with optional ECC and the ability to perform one double-precision floating-point operation per cycle per core; the consumer GeForce cards are artificially driver restricted to one DP operation per four cycles. With these features, combined with support for Visual Studio and C++, Nvidia targeted professional and commercial markets, as well as use in high performance computing.

Fermi is named after Italian physicist Enrico Fermi.

Current limitations and trade-offs

The quantity of on-board SRAM per ALU actually decreased proportionally compared to the previous G200 generation, despite the increase of the L2 cache from 256kB per 240 ALUs to 768kB per 512 ALUs, since Fermi has only 32768 registers per 32 ALUs (vs. 16384 per 8 ALUs), only 48kB of shared memory per 32 ALUs (vs. 16kB per 8 ALUs), and only 16kB of cache per 32 ALUs (vs. 8kB constant cache per 8 ALUs + 24kB texture cache per 24 ALUs). Parameters such as the number of registers can be found in the CUDA Compute Capability Comparison Table in the reference manual.

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