IBM ROMP
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History
The architectural work on the ROMP began in late spring of 1977, as a spin-off of IBM Research's 801 RISC processor (hence the "Research" in the acronym). Most of the architectural changes were for cost reduction, such as adding 16-bit instructions for byte-efficiency. The original ROMP had a 24-bit architecture, but the instruction set was changed to 32 bits a few years into the development.
The first chips were ready in early 1981, making ROMP the first industrial RISC. The processor was revealed at the International Solid-State Circuits Conference in 1984 ROMP first appeared in a commercial product as the processor for the IBM RT PC workstation, which was introduced in 1986. To provide examples for RT PC production, volume production of the ROMP and its MMU began in 1985. The delay between the completion of the ROMP design, and introduction of the RT PC was caused by overly ambitious software plans for the RT PC and its operating system (OS). This OS virtualized the hardware and could host multiple other operating systems. This technology, called virtualization, while commonplace in mainframe systems, only began to gain traction in smaller systems in the 21st century. An improved CMOS version of the ROMP was first used in the IBM 6152 Academic System workstation, and later in some models of the RT PC.
IBM Research used the ROMP in its Research Parallel Processor Prototype (RP3), an early experimental scalable shared-memory multiprocessor that supported up to 512 processors first detailed in 1985; and the CMOS version in its ACE, an experimental NUMA multiprocessor that was operational in 1988.
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Architecture
The ROMP's architecture was based on the original version of the IBM Research 801 minicomputer. The main differences were a larger word size (32 bits instead of 24), and the inclusion of virtual memory. The architecture supported 8-, 16-, and 32-bit integers, 32-bit addressing, and a 40-bit virtual address space. It had an instruction pointer register and sixteen 32-bit general-purpose registers. The microprocessor was controlled by 118 simple 16- and 32-bit instructions.
The ROMP's virtual memory has a segmented 40-bit (1 TB) address space consisting of 4,096 256 MB segments. The 40-bit virtual address is formed in the MMU by concatenating a 12-bit segment identifier with 28 low-order bits from a 32-bit ROMP-computed virtual address. The segment identifier is obtained from a set of 16 segment identifiers stored in the MMU, addressed by the four high-order bits of the 32-bit ROMP-computed virtual address.
Implementation
The ROMP is a scalar processor with a three-stage pipeline. In the first stage, if there are instructions in the 16-byte instruction prefetch buffer, an instruction was fetched, decoded, and operands from the general-purpose register file read. The instruction prefetch buffer read a 32-bit word from the memory whenever the ROMP was not accessing it. Instructions were executed in the second stage, and written back into the general-purpose register file in the third stage. The ROMP used a bypass network and appropriately scheduled the register file reads and writes to support back-to-back execution of dependent instructions. Most register-to-register instructions were executed in one cycle; of the 118 instructions, 84 had a single-cycle latency. The ROMP had an IBM-developed companion integrated circuit which was code-named Rosetta during development. Rosetta was a memory management unit (MMU), and it provided the ROMP with address translation facilities, a translation lookaside buffer, and a store buffer.
The ROMP and Rosetta were originally implemented in an IBM 2 μm silicon-gate NMOS technology with two levels of metal interconnect. The ROMP consists of 45,000 transistors and is 7.65 × 7.65 mm large (58.52 mm2), while Rosetta consists of 61,500 transistors and is 9.02 × 9.02 mm large (81.36 mm2). Both are packaged in 135-pin ceramic pin grid arrays. A CMOS version of the ROMP and Rosetta (called ROMP-C and Rosetta-C) was later developed.