Memory refresh

In a DRAM chip, each bit of memory data is stored as the presence or absence of an electric charge on a small capacitor on the chip. As time passes, the charges in the memory cells leak away, so without being refreshed, the stored data would eventually be lost. To prevent this, external circuitry periodically reads each cell and rewrites it, restoring the charge on the capacitor to its original level. Each memory refresh cycle refreshes a succeeding area of memory cells, thus repeatedly refreshing all the cells on the chip in a consecutive cycle. This process is typically conducted automatically in the background by the memory circuitry and is transparent to the user. While a refresh cycle is occurring, the memory is not available for normal read and write operations, but in modern memory, this overhead is not large enough to significantly slow down memory operation.

Static random-access memory (SRAM) is electronic memory that does not require refreshing. An SRAM memory cell requires four to six transistors, compared to a single transistor and a capacitor for DRAM; therefore, SRAM circuits require more area on a chip. As a result, data density is much lower in SRAM chips than in DRAM, which gives SRAM a higher price per bit. Therefore, DRAM is used for the main memory in computers, video game consoles, graphics cards and applications requiring large capacities and low cost. The need for memory refresh makes DRAM more complicated, but the density and cost advantages of DRAM justify this complexity.

Operation

While the memory is operating, each memory cell must be refreshed repetitively and within the maximum interval between refreshes specified by the manufacturer, usually in the millisecond region. Refreshing does not employ the normal memory operations (read and write cycles) used to access data, but specialized cycles called refresh cycles which are generated by separate counter circuits and interspersed between normal memory accesses.

The storage cells on a memory chip are laid out in a rectangular array of rows and columns. The read process in DRAM is destructive and removes the charge on the memory cells in an entire row, so there is a column of specialized latches on the chip called sense amplifiers, one for each column of memory cells, to temporarily hold the data. During a normal read operation, the sense amplifiers, after reading and latching the data, rewrite the data in the accessed row. This arrangement allows the normal read electronics on the chip to refresh an entire row of memory in parallel, significantly speeding up the refresh process. Although a normal read or write cycle refreshes a row of memory, normal memory accesses cannot be relied on to hit all the rows within the necessary time, necessitating a separate refresh process. Rather than use the normal read cycle in the refresh process, to save time, an abbreviated refresh cycle is used. The refresh cycle is similar to the read cycle, but executes faster for two reasons:

• For a refresh, only the row address is needed, so a column address doesn't have to be applied to the chip address circuits.
• Data read from the cells does not need to be fed into the output buffers or the data bus to send to the CPU.

To ensure that each cell gets refreshed within the refresh time interval, the refresh circuitry must perform a refresh cycle on each of the rows on the chip within the interval.

Types of refresh circuits

Although in some early systems the microprocessor controlled refresh, with a timer triggering a periodic interrupt that ran a subroutine that performed the refresh, this meant the microprocessor could not be paused, single-stepped, or put into energy-saving hibernation without stopping the refresh process and losing the data in memory. So in modern systems, refresh is handled by circuits in the memory controller, which may be embedded in the chip itself. Specialized DRAM chips, such as pseudostatic RAM (PSRAM), have all the refresh circuitry on the chip, and function like static RAM as far as the rest of the computer is concerned.

CPU-based refresh

Some early microprocessors (e.g., the Zilog Z80) provided special internal registers that could provide the Row Address Strobe (RAS) to refresh dynamic memory cells, the register being incremented on each refresh cycle. This could also be accomplished by other integrated circuits already being used in the system, if these already generate cycling accesses across RAM (e.g., the Motorola 6845). In CPUs such as the Z80, the availability of a RAS refresh was a big selling point due to its simplifying hardware design. Here, RAS refresh is signaled by a unique combination of address and control wires during operationally redundant clock cycles (T-States), i.e., during instruction decode and execution when the buses may not be required. Instead of the bus being inactive during such T-states, the refresh register would be presented on the address bus along with a combination of control signals to activate the refresh circuitry.

In early versions of the Z80, the ubiquity of 16 kB RAM chips having 128 rows and something of a lack of foresight resulted in the R register only incrementing over a 7-bit-wide range (0–127, 128 rows); the 8th bit could be set by the user, but would be left unchanged by the internal cycling. With the advent of 64 kbit+ DRAM chips (with 256 rows), extra circuitry or logic had to be built around the refresh signal to synthesize the missing 8th bit and prevent blocks of memory contents from being lost after a few milliseconds. In some contexts, it was possible to utilize interrupts and software to flip the 8th bit at the appropriate time and thus cover the entire range of the R register (256 rows). Another method, perhaps more universal but also more complex in terms of hardware, was to use an 8-bit counter chip, whose output would provide the refresh RAS address instead of the R register. The refresh signal from the CPU was used as the clock for this counter, resulting in the memory row being incremented with each refresh cycle. Later versions and licensed work-alikes of the Z80 core remedied the non-inclusion of the 8th bit in automatic cycling, and modern CPUs have greatly expanded on such basic provisioning to provide rich, all-in-one solutions for DRAM refresh.

Pseudostatic DRAM

Pseudostatic RAM (PSRAM or PSDRAM) is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to SRAM. It combines the high density of DRAM with the ease of use of true SRAM. PSRAM (made by Numonyx) is used in the Apple iPhone and other embedded systems.

Some DRAM components have a self-refresh standby mode. It is provided primarily to allow a system to suspend operation of its DRAM controller to save power without losing data stored in DRAM, whereas PSRAM allows operation without a separate DRAM controller. An embedded variant of PSRAM is sold by MoSys under the name 1T-SRAM. It is technically DRAM, but behaves much like SRAM, and is used in the GameCube and Wii consoles.

Refresh operation

Usually, the refresh circuitry consists of a refresh counter which contains the address of the row to be refreshed, which is applied to the chip's row address lines, and a timer that increments the counter to step through the rows. This counter may be part of the memory controller circuitry or on the memory chip itself. Two scheduling strategies have been used:

• Burst refresh – a series of refresh cycles are performed one after another until all the rows have been refreshed, after which normal memory accesses occur until the next refresh is required
• Distributed refresh – refresh cycles are performed at regular intervals, interspersed with memory accesses.

Burst refresh results in long periods when the memory is unavailable, so distributed refresh has been used in most modern systems, particularly in real-time systems. In distributed refresh, the interval between refresh cycles is

${\displaystyle \text{refresh cycle interval}=\text{refresh time}/\text{number of rows}}$

For example, DDR SDRAM has a refresh time of 64 ms and 8,192 rows, so the refresh cycle interval is 7.8 μs. In modern DDRx devices, only the distributed option is supported. On the other hand, LPDDRx devices still support burst refresh.

Asynchronous vs. synchronous refresh

Asynchronous DRAMs have three standard ways to provide refresh, selected by different patterns of signals on the column select (CAS) and row select (RAS) lines:

• RAS-only refresh – In this mode, the address of the row to refresh is provided by the address bus lines typically generated by external counters in the memory controller.
• CAS-before-RAS (CBR) refresh – In this mode, the on-chip counter keeps track of the row to be refreshed, and the external circuit merely initiates the refresh cycles. This mode uses less power because the memory address bus buffers don't have to be powered up. It is used in most modern computers.
• Hidden refresh – This is an alternate version of the CBR refresh cycle, which can be combined with a preceding read or write cycle. The refresh is done in parallel during the data transfer, saving time.

Synchronous DRAMs sample command and address signals on the edge of a clock. The refresh modes are:

• Auto-refresh (AR), a version of the CBR refresh. The DRAM chip uses its internal refresh counter to cycle through all the rows. The controller only needs to issue the AR command at a specified interval. AR requires substantial power for both the refresh and unrelated components, such as the DRAM's delay locked loop. Unlike DDRx devices, LPDDRx devices allow more selective per-bank auto-refresh to save power.
• Self-refresh (SR), a low-power mode for circumstances such as sleep mode. The chip ceases to use the external clock via the delay-locked loop and shuts down all I/O pins. An on-chip oscillator generates internal refresh cycles to preserve the data.

Refresh overhead

The fraction of time the memory spends on refresh, the refresh overhead, can be calculated from the system timing:

${\displaystyle \text{refresh overhead}=\frac{\text{time required for refresh}}{\text{refresh interval}}}$

For example, an SDRAM chip has 2¹³=8,192 rows, a refresh interval of 64 ms, the memory bus runs at 133 MHz, and the refresh cycle takes 4 clock cycles. The time for a refresh cycle is

${\displaystyle \text{length of refresh cycle}=4/f=\frac{4}{1.33({10}^8)\text{Hz}}=30\text{ns}}$

${\displaystyle \text{time required for refresh}=(\text{length of refresh cycle})(\text{rows})=(30\text{ns})(8192)=0.246\text{ms}}$

${\displaystyle \text{refresh overhead}=\frac{0.246\text{ms}}{64\text{ms}}=.0038}$

So less than 0.4% of the memory chip's time will be taken by refresh cycles. In SDRAM chips, the memory in each chip is divided into banks which are refreshed in parallel, saving further time. So the number of refresh cycles needed is the number of rows in a single bank, given in the specifications, which in the 2012 generation of chips has been frozen at 8,192.