Tagged architecture
Type of computer architecture
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Through Computer science, Word (computer architecture) and High-level programming language
Precursors
Some early systems use tagging of data in memory but do not have all of the characteristics now considered to be part of tagged architectures.
RCA 601
The RCA 601 has a 3-bit tag register and a 3-bit tag for every 24-bit half-word. Every instruction can request a test for equal or unequal tag, and cause a maskable interrupt if the specified match fails. There is no architectural connection between the tag and the contents of the half-word; it is strictly determined by the software.
Burroughs B5000, B5500, and B5700
The Burroughs B5000, B5500, and B5700 have 48-bit words with no appended tag field. However, while there are no tag fields for character, instruction, or numeric (floating point) words, every control word formats includes a 3-bit tag.
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Burroughs B6500 and successors
The Burroughs B6500 and its successors have a 3-bit tag for every word.
Architecture
In the von Neumann architecture, program memory and data memory are indistinguishable (as opposed to Harvard architecture, in which they are separate), which makes it critical for programs not to use memory contents for the wrong intent. Adding tags to the von Neumann architecture can prevent overwriting the program and prevent many more undesirable operations.
Notable examples of American tagged architectures were the Lisp machines, which had tagged pointer support at the hardware and opcode level, the Burroughs B6500 and successors, which have a data-driven tagged and descriptor-based architecture, and the non-commercial Rice Computer. Both the Burroughs and Lisp machine are examples of high-level language computer architectures, where the tagging is used to support types from a high-level language at the hardware level.
In addition to this, the original Xerox Smalltalk implementation used the least-significant bit of each 16-bit word as a tag bit: if it was clear then the hardware would accept it as an aligned memory address while if it was set it was treated as a (shifted) 15-bit integer. Current Intel documentation mentions that the lower bits of a memory address might be similarly used by some interpreter-based systems.
In the Soviet Union, the Elbrus series of supercomputers pioneered the use of tagged architectures in 1973.
The RISC-V J extension and memory-tagging extension (Zimt) both propose adding some support for tagged architecture at the instruction level.
CHERI (Capability Hardware Enhanced RISC Instructions) uses a tagged architecture to add capability-based addressing to several existing ISAs such as x86, MIPS, and RISC-V.
Intel i960 family
The Intel i960 family, including 80960MX had 33-bit memory. The 33rd bit was a tag that distinguished between 32-bit data words and 32-bit pointers to memory, and it blocked the use of calculated pointers to possibly access unauthorized memory addresses.