32 nm process

Toshiba produced commercial 32 GiB NAND flash memory chips with the 32 nm process in 2009. Intel and AMD produced commercial microchips using the 32 nm process in the early 2010s. IBM and the Common Platform also developed a 32 nm high-κ metal gate process. Intel began selling its first 32 nm processors using the Westmere architecture on 7 January 2010.

Since at least 1997, process nodes have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; none of the gate length, metal pitch, or gate pitch on a "32 nm" device are thirty-two nanometers.

The 28 nm node is an intermediate half-node die shrink that appeared in production in 2010. It requires twice the number of design rules for ensuring reliability in manufacturing as 80 nm. According to a 2016 presentation by Sophie Wilson, 28 nm has the lowest cost per logic gate and has slowly risen since then. TSMC has offered 28 nm production using high-K metal gate process technology. GlobalFoundries offered "28SLPe" ("28 nm Super Low Power").

The successor to 32 nm was 22 nm, per the International Technology Roadmap for Semiconductors. Intel began mass production of 22 nm semiconductors in late 2011, and announced the release of its first commercial 22 nm devices in April 2012. TSMC bypassed 32 nm, jumping from 40 nm in 2008 to 28 nm in 2011.

Technology demos

Prototypes using 32 nm technology first emerged in the mid-2000s. In 2004, IBM demonstrated a 0.143 μm² SRAM cell with a poly gate pitch of 135 nm, produced using electron-beam lithography and photolithography on the same layer. It was observed that the cell's sensitivity to input voltage fluctuations degraded significantly at such a small scale. In October 2006, the Interuniversity Microelectronics Centre (IMEC) demonstrated a 32 nm flash patterning capability based on double patterning and immersion lithography. The necessity of introducing double patterning and hyper-NA tools to reduce memory cell area offset some of the cost advantages of moving to this node from the 45 nm node. TSMC similarly used double patterning combined with immersion lithography to produce a 32 nm node 0.183 μm² six-transistor SRAM cell in 2005.

Intel Corporation revealed its first 32 nm test chips to the public on 18 September 2007 at the Intel Developer Forum. The test chips had a cell size of 0.182 μm², used a second-generation high-κ gate dielectric and metal gate, and contained almost two billion transistors. 193 nm immersion lithography was used for the critical layers, while 193 nm or 248 nm dry lithography was used on less critical layers. The critical pitch was 112.5 nm.

In January 2011, Samsung completed development of the industry's first DDR4 SDRAM module using a process technology with a size between 30 nm and 39 nm. The module could reportedly achieve data transfer rates of 2.133 Gbit/s at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent 30 nm-class process technology with speeds of up to 1.6 Gbit/s. The module used pseudo open drain (POD) technology, specially adapted to allow DDR4 SDRAM to consume just half the current of DDR3 when reading and writing data.