DIMM

Form factors

Widths

DIMMs come in a number of board sizes. In order of descending size: DIMM, SO-DIMM, MiniDIMM, and MicroDIMM.

Regular DIMMs are generally 133.35 mm in length, while SO-DIMMs are generally 67.6 mm in length.

DIMM

SO-DIMM

A SO-DIMM (pronounced "so dim" , also spelled SODIMM) or small outline DIMM, is a smaller alternative to a DIMM, being roughly half the physical size of a regular DIMM. The first SO-DIMMs had 72 pins and were introduced by JEDEC in 1997. Before its introduction, many laptops would use proprietary RAM modules which were expensive and hard to find.

SO-DIMMs are often used in computers that have limited space, which include laptops, notebook computers, small-footprint personal computers such as those based on Nano-ITX motherboards, high-end upgradable office printers, and networking hardware such as routers and NAS devices. They are usually available with the same size data path and speed ratings of the regular DIMMs though normally with smaller capacities.

Mini-DIMM

Mini-DIMM has a longer but a narrower profile than SO-DIMM. Mini-DIMM has more power and ground pins compared to SO-DIMM that makes them often used in telecom, networking, and industrial applications.

MicroDIMM

MicroDIMM is the smallest DIMM factor and is half the physical size of SO-DIMM. MicroDIMMs are often used in lightweight laptops and printers. MicroDIMM has only been iterated to DDR2.

Connector

Different generations of memory are not interchangeable: neither forward compatible nor backward compatible. To make this difference clear and avoid any confusion, their DIMM modules all have different pin counts and/or different notch positions. DDR5 SDRAM is the most recent type of DDR memory and has been in use since 2020.

DIMM

• 100-pin: printer SDRAM and printer ROM (e.g., PostScript)
• 168-pin: SDR SDRAM, sometimes used for FPM/EDO DRAM in workstations or servers, may be 3.3 or 5 V
• 184-pin: DDR SDRAM
• 200-pin: FPM/EDO DRAM in some Sun workstations and servers
• 240-pin: DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM
• 278-pin: HP high density SDRAM
• 288-pin: DDR4 SDRAM and DDR5 SDRAM

SO-DIMM

• 072-pin: FPM DRAM and EDO DRAM; different pin configuration from 72-pin SIMM
• 144-pin: SDR SDRAM, sometimes used for DDR2 SDRAM
• 200-pin: DDR SDRAM and DDR2 SDRAM
• 204-pin: DDR3 SDRAM
• 260-pin: DDR4 SDRAM
• 260-pin: UniDIMMs carrying either DDR3 or DDR4 SDRAM; differently notched than DDR4 SO-DIMMs
• 262-pin: DDR5 SDRAM

MiniDIMM

• 244-pin: DDR2 SDRAM
• 244-pin: DDR3 SDRAM
• 244-pin: DDR4 UDIMM
• 288-pin: DDR4 RDIMM

MicroDIMM

• 144-pin: SDRAM
• 172-pin: DDR SDRAM
• 214-pin: DDR2 SDRAM

Besides pin count there are also physical notches to differentiate the incompatible types of DIMM. For example, the ancient 168-pin SDR SDRAM had different voltage ratings (5.0 V or 3.3 V) and a difference of registered (buffered) vs unbuffered. As a result it has two notch positions to prevent the insertion of the wrong type of module.

Heights

Several form factors are commonly used in DIMMs. Single Data Rate Synchronous DRAM (SDR SDRAM) DIMMs were primarily manufactured in 1.5 inches (38 mm) and 1.7 inches (43 mm) heights, with the nominal value being 30 millimetres (1.2 in). When 1U rackmount servers started becoming popular, these form factor registered DIMMs had to plug into angled DIMM sockets to fit in the 1.75 inches (44 mm) high box. To alleviate this issue, the next standards of DDR DIMMs were created with a "low profile" (LP) height of around 1.2 inches (30 mm). These fit into vertical DIMM sockets for a 1U platform.

With the advent of blade servers, angled slots have once again become common in order to accommodate LP form factor DIMMs in these space-constrained boxes. This led to the development of the Very Low Profile (VLP) form factor DIMM with a height of around 18 millimetres (0.71 in). These will fit vertically in ATCA systems.

Very similar height levels are used for SO-DIMM, Mini-DIMM and Micro-DIMM.

Notes:

• Low profile (LP) is not a JEDEC standard.
• The full JEDEC standards also regulate factors such as thickness.
• SO-DIMMs for DDR4 and DDR5 maintain the traditional height of 30.00±0.15 mm; see JEDEC MO-310A and MO-337B. The height increase for "full height" DIMM does not apply to SO-DIMM.
• It is common for higher-end consumer DDR4 DIMMs to exceed the JEDEC full height due to the use of an added heat sink. Some heat sinks add as little as 1 millimetre (0.039 in) while others add up to 5 millimetres (0.20 in).

Similar connectors

As of Q2 2017, Asus has had a PCIe based "DIMM.2", which has a similar socket to DDR3 DIMMs and is used to put in a module to connect up to two M.2 NVMe solid-state drives. However, it cannot use common DDR type ram and does not have much support from other than Asus.

Components

Organization

Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with up to nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in bits. High-capacity DIMMs such as 256 GB DIMMs can have up to 19 chips per side.

In the case of "×4" registered DIMMs, the data width per side is 36 bits; therefore, the memory controller (which requires 72 bits) needs to address both sides at the same time to read or write the data it needs. In this case, the two-sided module is single-ranked. For "×8" registered DIMMs, each side is 72 bits wide, so the memory controller only addresses one side at a time (the two-sided module is dual-ranked).

The above example applies to ECC memory that stores 72 bits instead of the more common 64. There would also be one extra chip per group of eight, which is not counted.

Ranking

Sometimes, memory modules are designed with two or more independent sets of DRAM chips connected to the same address and data buses; each such set is called a rank. Of the ranks that share the same memory slot, i.e. on the same module, only one rank may be accessed at any given time. The rank to be accessed is specified by activating its chip select (CS) signal, while the other ranks on the same module are deactivated for the duration of the operation by having their corresponding CS signals deactivated.

After a memory word is fetched, the memory is typically inaccessible for an extended period of time while the sense amplifiers are charged for access of the next cell. These amplifiers typically have 3 cycles of idle time for recharging between accesses. By interleaving the memory (e.g. cells 0, 4, 8, ... are stored in one rank, cells 1, 5, 9, ... in another rank, and so on), sequential memory accesses can be performed more rapidly by alternating which rank is active, thus overlapping the active memory access with recharge time for the inactive ranks.

As of 2025, DIMMs are commonly manufactured with one, two, or four ranks per module. Consumer DIMM vendors have begun to distinguish between single- and dual-ranked DIMMs since around 2020.

DIMMs are often referred to as "single-sided" or "double-sided" to describe whether the DRAM chips are located on one or both sides of the module's printed circuit board (PCB). However, these terms may cause confusion, as the physical layout of the chips does not necessarily relate to how they are logically organized or accessed. Indeed, quad-ranked DIMMs exist.

JEDEC decided that the terms "dual-sided", "double-sided", or "dual-banked" were not correct when applied to registered DIMMs (RDIMMs).

Multiplexed Rank DIMM (MRDIMM) allow data from multiple ranks to be transmitted on the same channel. It was announced for DDR5 in July 2024 and is expected to be backwards compatible with DDR5 RDIMM.

SPD EEPROM

A DIMM's capacity and other operational parameters may be identified with serial presence detect (SPD), an additional chip which contains information about the module type and timing for the memory controller to be configured correctly. The SPD EEPROM connects to the System Management Bus and may also contain thermal sensors (TS-on-DIMM).

Features

Speeds

For various technologies, there are certain bus and device clock frequencies that are standardized; there is also a decided nomenclature for each of these speeds for each type.

DIMMs based on Single Data Rate (SDR) DRAM have the same bus frequency for data, address and control lines. DIMMs based on Double Data Rate (DDR) DRAM have data but not the strobe at double the rate of the clock; this is achieved by clocking on both the rising and falling edge of the data strobes. Power consumption and voltage gradually became lower with each generation of DDR-based DIMMs.

Another influence is Column Access Strobe (CAS) latency, or CL, which affects memory access speed. This is the delay time between the READ command and the moment data is available. See main article CAS/CL and memory timing.

Error correction

ECC DIMMs are those that have extra data bits which can be used by the system memory controller to detect and correct errors. There are numerous ECC schemes, but perhaps the most common is Single Error Correct, Double Error Detect (SECDED) which uses an extra byte per 64-bit word. ECC modules usually carry a multiple of 9 instead of a multiple of 8 chips as a result.

Register/buffer

It is electrically demanding for a memory controller to drive many DIMMs. Registered DIMMs add a hardware register to the clock, address, and command lines so that the signals are refreshed on the DIMM, allowing a reduced load on the memory controller. Variants include LRDIMM with all lines buffered and CUDIMM/CSODIMM with only the clock signal buffered. The register feature often occurs with ECC, but they do not actually depend on each other and can occur independently.