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Ferroelectric RAM

Novel type of computer memory

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Through Dielectric and Non-volatile memory

FeRAM's advantages over Flash include: lower power usage, faster write speeds and a much greater maximum read/write endurance (about 1010 to 1015 cycles). FeRAMs have data retention times of more than 10 years at +85 °C (and decades at lower temperatures). The primary disadvantages of FeRAM are much lower storage densities than flash devices, storage capacity limitations and higher cost. Like DRAM, FeRAM's read process is destructive, necessitating a write-after-read architecture.

History

Ferroelectric RAM was proposed by MIT graduate student Dudley Allen Buck in his master's thesis, Ferroelectrics for Digital Information Storage and Switching, published in 1952.

In 1955, Bell Telephone Laboratories was experimenting with ferroelectric-crystal memories. Following the introduction of metal–oxide–semiconductor (MOS) dynamic random-access memory (DRAM) chips in the early 1970s, development of FeRAM began in the late 1980s. Work was done in 1991 at NASA's Jet Propulsion Laboratory (JPL) on improving methods of read out, including a novel method of non-destructive readout using pulses of UV radiation.

FeRAM was commercialized in the mid-1990s. In 1994, video game company Sega used FeRAM chips to store saved games in Sonic the Hedgehog 3, which shipped several million game cartridges that year. In 1996, Samsung Electronics introduced a 4 Mb FeRAM chip fabricated using NMOS logic. In 1998, Hyundai Electronics (now SK Hynix) also commercialized FeRAM technology. The earliest known commercial product to use FeRAM is Sony's PlayStation 2 Memory Card (8 MB), released in 2000. The Memory Card's microcontroller (MCU) manufactured by Toshiba contained 32 kb (4 kB) embedded FeRAM fabricated using a 500 nm complementary MOS (CMOS) process.

In 1999 Fujitsu began producing standalone FeRAMs, as well as specialized chips (e.g. chips for smart cards) with embedded FeRAMs for Ramtron. In 2010 Ramtron switched to Texas Instruments and IBM.

In 2024–2025 ferroelectric RAM research was driven by HfO₂-based materials for CMOS compatibility, scalability to <10 nm, and integration into advanced nodes (22–28 nm). Cycle counts exceeded 10¹², with reduced power requirements.

Prototypes offered 9–16 Mb arrays with 10¹² endurance and 5–7 ns read/write.

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