ILLIAC

ORDVAC

ORDVAC was the first of two computers built under contract at the University of Illinois. ORDVAC was completed the spring of 1951 and checked out in the summer. In the fall it was delivered to the US Army's Aberdeen Proving Grounds and was checked out in roughly one week. As part of the contract, funds were provided to the University of Illinois to build a second identical computer known as ILLIAC I.

ILLIAC I

ILLIAC I was built at the University of Illinois based on the same design as the ORDVAC. It was the first von Neumann architecture computer built and owned by an American university. It was put into service on September 22, 1952.

ILLIAC I was built with 2,800 vacuum tubes and weighed about 5 tons. By 1956 it had gained more computing power than all computers in Bell Labs combined. Data was represented in 40-bit words, of which 1,024 could be stored in the main memory, and 12,800 on drum memory.

Immediately after the 1957 launch of Sputnik, the ILLIAC I was used to calculate an ephemeris of the satellite's orbit, later published in Nature.

ILLIAC I was decommissioned in 1963 when ILLIAC II (see below) became operational.

ILLIAC II

The ILLIAC II was the first transistorized and pipelined supercomputer built by the University of Illinois. ILLIAC II and the IBM 7030 Stretch were two competing projects to build first-generation transistorized supercomputers . ILLIAC II was an asynchronous logic design. At its inception in 1958 it was 100 times faster than competing machines of that day. It became operational in 1962, two years later than expected.

ILLIAC II had 8192 words of core memory, backed up by 65,536 words of storage on magnetic drums. The core memory access time was 1.8 to 2 μs. The magnetic drum access time was 7 μs. A "fast buffer" was also provided for storage of short loops and intermediate results (similar in concept to what is now called cache). The "fast buffer" access time was 0.25 μs.

The word size was 52 bits. Floating-point numbers used a format with 7 bits of exponent (power of 4) and 45 bits of mantissa. Instructions were either 26 bits or 13 bits long, allowing packing of up to four instructions per memory word. The pipelined functional units were called advanced control, delayed control, and interplay. The computer used Muller speed-independent circuitry (i.e. Muller C-Element) for a portion of the control circuitry.

In 1963 Donald B. Gillies (who designed the control) used the ILLIAC II to find three Mersenne primes, with 2917, 2993, and 3376 digits - the largest primes known at the time.

Hideo Aiso (相磯秀夫; 1932-2025) from Japan participated in the development program and designed the arithmetic logic unit from September 1960.

ILLIAC III

The ILLIAC III was a fine-grained SIMD pattern recognition computer built by the University of Illinois in 1966.

This ILLIAC's initial task was image processing of bubble chamber experiments used to detect nuclear particles. Later it was used on biological images. The machine was destroyed in a fire, caused by a Variac shorting on one of the wooden-top benches, in 1968.

ILLIAC IV

The ILLIAC IV was one of the first attempts at a massively parallel computer. Key to the design as conceived by Daniel Slotnick, the director of the project, was fairly high parallelism with up to 256 processors, used to allow the machine to work on large data sets in what would later be known as array processing. The machine was to have four quadrants. Each quadrant had a Control Unit (CU) and 64 Processor Elements (PEs). Originally Texas Instruments made a commitment to build the Processing Elements (PEs) out of large-scale integrated (LSI) circuits. Several years into the project, TI backed out and said that they could not produce the LSI chips at the contracted price. This required a complete redesign using medium-scale integrated circuits, leading to large delays and greatly increasing costs. This also led to scaling the system back from four quadrants to a single quadrant, since the MSI version was going to be many times larger than the LSI version would have been. This led to the CU having pull out 'cards' that were on the order of two feet square. For the PEs what should have been chips about 1 inch in diameter were now roughly 6 by 10 inches. Space, power and air conditioning (not to mention budget) did not allow for a four-quadrant machine. The machine was 10' high, 8' deep and 50' long. There could be 10-12 instructions being sent from the CU on the wires to the PEs at any time. The power supplies for the machine were so large that it required designing a single-tongue fork lift to remove and reinstall the power supply. The power supply buss bars on the machine spanned distances greater than three feet, and were octopus-like in design. Thick copper, the busses were coated in epoxy that often cracked resulting in shorts and an array of other issues. ILLIAC IV was designed by Burroughs Corporation and built in quadrants in Great Valley, Pennsylvania during the years of 1967 through 1972. It had a traditional one-address accumulator architecture, rather than the revolutionary stack architecture pioneered by Burroughs in the 5500/6500 machines. ILLIAC IV was designed in fact to be a "back-end processor" to a B6700. The cost overruns caused by not getting the LSI chips and other design errors by Burroughs (the control unit was built with positive logic and the PEs with negative logic, etc.) made the project untenable.

Starting in 1970, the machine became the subject of student demonstrations at the University of Illinois. First, that the project had been secretly created on campus. When this claim proved to be false, the focus shifted to the role of universities in secret military research. Slotnick was not in favor of running classified programs on the machine. ARPA wanted the machine room encased in copper to prevent off-site snooping of classified data. Slotnick refused to do that. He went further and insisted that all research performed on ILLIAC IV would be published. If the machine had been installed in Urbana this would have been the case. However, two things caused the machine to be delivered to NASA Ames Research Center. One was that Slotnick was concerned that the physical presence of the machine on campus might attract violence on the part of student radicals. This and the requirement to do secret research with the machine led ARPA to move the machine to NASA Ames Research Center, where it was installed in a secure environment. The machine was never delivered to Illinois. In 1972, when the first (and only quadrant) was operational at NASA, it was 13 times faster than any other machine operating at the time. The Control Unit, a few PEs, and its 10-megabyte drives may be seen today at the Computer History Museum in California.

CEDAR

CEDAR was a hierarchical shared-memory supercomputer completed in 1988. The development team was led by Professor David Kuck. This SMP (symmetric multiprocessing) system embodied advances in interconnection networks, control unit support of parallelism, optimizing compilers and parallel algorithms and applications. It is occasionally referred to as ILLIAC V.

ILLIAC 6

Design of the ILLIAC 6 began in early 2005 at the University of Illinois Urbana-Champaign led by Luddy Harrison. It was intended as a 65536-node communications supercomputer utilizing commodity digital signal processors as the computation nodes. It was designed for over 1.2 quadrillion multiply-accumulate operations per second and a bi-sectional bandwidth of over 4 terabytes per second.

Trusted ILLIAC

The Trusted ILLIAC was completed in 2006 at the University of Illinois Urbana-Champaign's Coordinated Science Laboratory and Information Trust Institute. It was a 256-node Linux cluster, with each node having two processors.

Trusted ILLIAC nodes contained onboard FPGAs to enable smart compilers and programming models, system assessment and validation, configurable trust mechanisms, automated fault management, on-line adaptation, and numerous other configurable trust frameworks. The nodes each had access to 8 GB memory on a 6.4 GB/s bus, and were connected via 8 GB/s PCI-Express to the FPGAs. A 2.5 GB/s InfiniBand network provides the internode connectivity. The system was constructed using the help and support of Hewlett-Packard, AMD and Xilinx.