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Motorola 68060

Motorola 680x0 microprocessor, released in April 1994

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The 68060 is the last development of the 68000 family for general purpose use, abandoned in favor of the PowerPC chips. Two derivatives were produced, the 68LC060 (low cost), which lacked the floating-point unit (FPU), and the 68EC060 (embedded controller), which removed both the FPU and memory management unit (MMU).

Architecture

The 68060 shares most architectural features with the P5 Pentium. Both have a very similar superscalar in-order dual instruction pipeline configuration, and an instruction decoder that breaks down complex instructions into simpler ones before execution, described publicly as "two four-stage RISC engines [that] execute the fixed-format instructions emitted by the instruction converter". Such translated instructions are stored in a 16-entry FIFO buffer, with more complex 68000 instructions occupying multiple entries, and with some of the most complex instructions causing trap conditions for software to handle accordingly.

A significant difference to the Pentium is that the 68060 FPU is not pipelined and is therefore up to three times slower than the Pentium in floating point applications. In contrast to that, integer multiplications and bit shifting instructions are significantly faster on the 68060. The 68060 has the ability to execute simple instructions in the address generation unit (AGU) and thereby supply the result two cycles before the ALU. In the development of the 68060, large amounts of commercial compiled code were analyzed for clues as to which instructions would be the best candidates for performance optimization.

Against the Pentium, the 68060 can perform better on mixed code; Pentium's decoder cannot issue an FP instruction every opportunity and hence the FPU is not superscalar as the ALUs were. If the 68060's non-pipelined FPU can accept an instruction, it can be issued one by the decoder. This means that optimizing for the 68060 is easier: no rules prevent FP instructions from being issued whenever was convenient for the programmer other than well understood instruction latencies. Nonetheless, with properly optimized and scheduled code, the Pentium's FPU is capable of double the clock for clock throughput of the 68060's FPU.

There is an LC (Low-Cost) version, without an FPU and EC (Embedded Controller), without MMU and FPU. The 68060 design was led by Joe Circello.

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