NAND gate

Logic

The function NAND(a₁, a₂, ..., a_n) is logically equivalent to NOT(a₁ AND a₂ AND ... AND a_n).

One way of expressing A NAND B is ${\displaystyle \overline{A\wedge B}}$, where the symbol ${\displaystyle \wedge }$ signifies AND and the bar signifies the negation of the expression under it: in essence, simply ${\displaystyle {\displaystyle \mathrm{\neg }(A\wedge B)}}$.

Implementations

The basic implementations can be understood from the image on the left below: If either of the switches S1 or S2 is open, the pull-up resistor R will set the output signal Q to 1 (high). If S1 and S2 are both closed, the pull-up resistor will be overridden by the switches, and the output will be 0 (low).

In the depletion-load NMOS logic realization in the middle below, the switches are the transistors T2 and T3, and the transistor T1 fulfills the function of the pull-up resistor.

In the CMOS realization on the right below, the switches are the n-type transistors T3 and T4, and the pull-up resistor is made up of the p-type transistors T1 and T2, which form the complement of transistors T3 and T4.

In CMOS, NAND gates are more efficient than NOR gates. This is due to the faster charge mobility in n-MOSFETs compared to p-MOSFETs, so that the parallel connection of two p-MOSFETs (T1 and T2) realised in the NAND gate is more favourable than their series connection in the NOR gate. For this reason, NAND gates are generally preferred over NOR gates in CMOS circuits.

Hardware design and pinout

NAND gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs.

The standard, 4000 series, CMOS IC is the 4011, which includes four independent, two-input, NAND gates. These devices are available from many semiconductor manufacturers. These are usually available in both through-hole DIL and SOIC formats. Datasheets are readily available in most datasheet databases.

The standard two-, three-, four- and eight-input NAND gates are available:

• CMOS
  • 4011: Quad two-input NAND gate
  • 4023: Triple three-input NAND gate
  • 4012: Dual four-input NAND gate
  • 4068: Mono eight-input NAND gate
• TTL
  • 7400: Quad two-input NAND gate
  • 7410: Triple three-input NAND gate
  • 7420: Dual four-input NAND gate
  • 7430: Mono eight-input NAND gate

Functional completeness

The NAND gate has the property of functional completeness, which it shares with the NOR gate. That is, any other logic function (AND, OR, etc.) can be implemented using only NAND gates. An entire processor can be created using NAND gates alone. In TTL ICs using multiple-emitter transistors, it also requires fewer transistors than a NOR gate.

As NOR gates are also functionally complete, if no specific NAND gates are available, one can be made from NOR gates using NOR logic.