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POWER9

2017 family of multi-core microprocessors by IBM

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Summit, the ninth fastest supercomputer in the world (based on the Top500 list) as of June 2024, is based on POWER9, while also using Nvidia Tesla GPUs as accelerators.

Design

Core

The POWER9 core comes in two variants, a four-way multithreaded one called SMT4 and an eight-way one called SMT8. The SMT4- and SMT8-cores are similar, in that they consist of a number of so-called slices fed by common schedulers. A slice is a rudimentary 64-bit single-threaded processing core with load store unit (LSU), integer unit (ALU) and a vector scalar unit (VSU, doing SIMD and floating point). A super-slice is the combination of two slices. An SMT4-core consists of a 32 KiB L1 cache (1 KiB = 1024 bytes), a 32 KiB L1 data cache, an instruction fetch unit (IFU) and an instruction sequencing unit (ISU) which feeds two super-slices. An SMT8-core has two sets of L1 caches and, IFUs and ISUs to feed four super-slices. The result is that the 12-core and 24-core versions of POWER9 each consist of the same number of slices (96 each) and the same amount of L1 cache.

A POWER9 core, whether SMT4 or SMT8, has a 12-stage pipeline (five stages shorter than its predecessor, the POWER8), but aims to retain the clock frequency of around 4 GHz. It will be the first to incorporate elements of the Power ISA v.3.0 that was released in December 2015, including the VSX-3 instructions. The POWER9 design is made to be modular and used in more processor variants and used for licensing, on a different fabrication process than IBM's. On chip are co-processors for compression and cryptography, as well as a large low-latency eDRAM L3 cache.

The POWER9 comes with a new interrupt controller architecture called "eXternal Interrupt Virtualization Engine" (XIVE) which replaces a much simpler architecture that was used in POWER4 through POWER8. XIVE will also be used in Power10.

Scale out / scale up

  • IBM POWER9 SO – scale-out variant, optimized for dual socket computers with up to 120 GB/s bandwidth (1 GB = 1 billion bytes) to directly attached DDR4 memory (targeted for release in 2017)
  • IBM POWER9 SU – scale-up variant, optimized for four sockets or more, for large NUMA machines with up to 230 GB/s bandwidth to buffered memory (uses "25.6 GHz" signaling with the PowerAXON 25 GT/sec Link interface)

Both POWER9 variants can ship in versions with some cores disabled due to yield reasons, as such Raptor Computing Systems first sold 4-core chips, and even IBM initially sold its AC922 systems with no more than 22-core chips, even though both types of chips have 24 cores on their dies.

I/O

A lot of facilities are on-chip for helping with massive off-chip I/O performance:

  • The SO variant has integrated DDR4 controllers for directly attached RAM, while the SU variant will use the off-chip Centaur architecture introduced with POWER8 to include high performance eDRAM L4 cache and memory controllers for DDR4 RAM.
  • The Bluelink interconnects for close attachment of graphics co-processors from Nvidia (over NVLink v.2) and OpenCAPI accelerators.
  • General purpose PCIe v.4 connections for attaching regular ASICs, FPGAs and other peripherals as well as CAPI 2.0 and CAPI 1.0 devices designed for POWER8.
  • Multiprocessor (symmetric multiprocessor system) links to connect other POWER9 processors on the same motherboard, or in other closely attached enclosures.

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