Transactional memory

Hardware vs. software

The abstraction of atomicity in transactional memory requires a hardware mechanism to detect conflicts and undo any changes made to shared data. Hardware transactional memory systems may comprise modifications in processors, cache and bus protocol to support transactions. Speculative values in a transaction must be buffered and remain unseen by other threads until commit time. Large buffers are used to store speculative values while avoiding write propagation through the underlying cache coherence protocol. Traditionally, buffers have been implemented using different structures within the memory hierarchy such as store queues or caches. Buffers further away from the processor, such as the L2 cache, can hold more speculative values (up to a few megabytes). The optimal size of a buffer is still under debate due to the limited use of transactions in commercial programs. In a cache implementation, the cache lines are generally augmented with read and write bits. When the hardware controller receives a request, the controller uses these bits to detect a conflict. If a serializability conflict is detected from a parallel transaction, then the speculative values are discarded. When caches are used, the system may introduce the risk of false conflicts due to the use of cache line granularity. Load-link/store-conditional (LL/SC) offered by many RISC processors can be viewed as the most basic transactional memory support; however, LL/SC usually operates on data that is the size of a native machine word, so only single-word transactions are supported. Although hardware transactional memory provides maximal performance compared to software alternatives, limited use has been seen at this time.

Software transactional memory provides transactional memory semantics in a software runtime library or the programming language, and requires minimal hardware support (typically an atomic compare and swap operation, or equivalent). As the downside, software implementations usually come with a performance penalty, when compared to hardware solutions. Hardware acceleration can reduce some of the overheads associated with software transactional memory.

Owing to the more limited nature of hardware transactional memory (in current implementations), software using it may require fairly extensive tuning to fully benefit from it. For example, the dynamic memory allocator may have a significant influence on performance and likewise structure padding may affect performance (owing to cache alignment and false sharing issues); in the context of a virtual machine, various background threads may cause unexpected transaction aborts.

History

One of the earliest implementations of transactional memory was the gated store buffer used in Transmeta's Crusoe and Efficeon processors. However, this was only used to facilitate speculative optimizations for binary translation, rather than any form of speculative multithreading, or exposing it directly to programmers. Azul Systems also implemented hardware transactional memory to accelerate their Java appliances, but this was similarly hidden from outsiders.

Sun Microsystems implemented hardware transactional memory and a limited form of speculative multithreading in its high-end Rock processor. This implementation proved that it could be used for lock elision and more complex hybrid transactional memory systems, where transactions are handled with a combination of hardware and software. The Rock processor was canceled in 2009, just before the acquisition by Oracle; while the actual products were never released, a number of prototype systems were available to researchers.

In 2009, AMD proposed the Advanced Synchronization Facility (ASF), a set of x86 extensions that provide a very limited form of hardware transactional memory support. The goal was to provide hardware primitives that could be used for higher-level synchronization, such as software transactional memory or lock-free algorithms. However, AMD has not announced whether ASF will be used in products, and if so, in what timeframe.

More recently, IBM announced in 2011 that Blue Gene/Q had hardware support for both transactional memory and speculative multithreading. The transactional memory could be configured in two modes; the first is an unordered and single-version mode, where a write from one transaction causes a conflict with any transactions reading the same memory address. The second mode is for speculative multithreading, providing an ordered, multi-versioned transactional memory. Speculative threads can have different versions of the same memory address, and hardware implementation keeps track of the age for each thread. The younger threads can access data from older threads (but not the other way around), and writes to the same address are based on the thread order. In some cases, dependencies between threads can cause the younger versions to abort.

Intel's Transactional Synchronization Extensions (TSX) is available in some of the Skylake processors. It was earlier implemented in Haswell and Broadwell processors as well, but the implementations turned out both times to be defective and support for TSX was disabled. The TSX specification describes the transactional memory API for use by software developers, but withholds details on technical implementation. ARM architecture has a similar extension.

As of GCC 4.7, an experimental library for transactional memory is available which utilizes a hybrid implementation. The PyPy variant of Python also introduces transactional memory to the language.

C++ has a "Transactional Memory Technical Specification" (TM TS) which is an experimental fork of the language implementing transactional memory as a core feature of the language. It introduces "atomic blocks" (either all statements occur or nothing occurs) and "synchronized blocks" (executed in single total order with all synchronized blocks). It introduces the following keywords:

• atomic_cancel: Declares an atomic block that rolls back on exception.
• atomic_commit: Declares an atomic block that commits on exception.
• atomic_noexcept: Declares an atomic block that aborts on exception.
• synchronized: Declares a synchronized block that executes in single total order with all synchronized blocks. Compare with Java synchronized blocks, which have a "monitor object" or "intrinsic lock", and where only one thread can execute a specific section of code.
• transaction_safe: Declares a function to be transaction-safe.
• transaction_safe_dynamic: Declares a virtual function to be transaction-safe.

Progress on the development of the Transactional Memory TS has stalled as of 2026, while the last known working draft was a revision made in 2022.

Available implementations

• Hardware:
  • Arm Transactional Memory Extension (TME)
  • Blue Gene/Q processor from IBM (Sequoia supercomputer)
  • IBM zEnterprise EC12, the first commercial server to include transactional memory processor instructions
  • Intel's Transactional Synchronization Extensions (TSX), available in select Haswell-based processors and newer until be removed in Comet Lake
  • IBM POWER8 and 9, removed in Power10 (Power ISA v.3.1)
  • Rock processor (canceled by Oracle)
• Software:
  • Vega 2 from Azul Systems
  • STM Monad in the Glasgow Haskell Compiler
  • STMX in Common Lisp
  • Refs in Clojure
  • gcc 4.7+ for C/C++
  • C++ Transactional Memory Technical Specification (experimental)
  • PyPy
  • Part of the picotm Transaction Framework for C
  • The TVar in concurrent-ruby, a concurrency library for Ruby
  • Verse