90 nm process

It was commercialized by the 2003–2005 timeframe, by semiconductor companies including Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology.

The origin of the 90 nm value is historical; it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).

The 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.

The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; neither gate length, metal pitch or gate pitch on a "90nm" device is ninety nanometers.

History

A 90 nm silicon MOSFET was fabricated by Iranian engineer Ghavam Shahidi (later IBM director) with D.A. Antoniadis and H.I. Smith at MIT in 1988. The device was fabricated using X-ray lithography.

Toshiba, Sony and Samsung developed a 90 nm process during 2001–2002, before being introduced in 2002 for Toshiba's eDRAM and Samsung's 2 Gb NAND flash memory. IBM demonstrated a 90 nm silicon-on-insulator (SOI) CMOS process, with development led by Shahidi, in 2002. The same year, Intel demonstrated a 90 nm strained-silicon process. Fujitsu commercially introduced its 90 nm process in 2003 followed by TSMC in 2004.

Gurtej Singh Sandhu of Micron Technology initiated the development of atomic layer deposition high-k films for DRAM memory devices. This helped drive cost-effective implementation of semiconductor memory, starting with 90 nm node DRAM.

Intel's 90nm process has a transistor density of 1.45 million transistors per square millimeter (MTr/mm2).