Cell (processor)

Overview

The Cell Broadband Engine, or "Cell" as it is more commonly known, is a microprocessor intended as a hybrid of conventional desktop processors (such as the Athlon 64 and the Core 2 families) and more specialized high-performance processors (such as the NVIDIA and ATI graphics processing units [GPUs]). The longer name indicates its intended use, namely, as a component in current and future online distribution systems; as such, it may be used in high-definition displays and recording equipment, as well as HDTV systems. In addition, the processor may be suited to digital imaging systems (e.g., medical and scientific) and physical simulation (e.g., scientific and structural engineering modeling). As used in the PlayStation 3, the processor has 250 million transistors.

In a simple analysis, the Cell processor can be divided into four components:

• external input and output structures
• the main processor, called the Power Processing Element (PPE)—a two-way simultaneous-multithreaded PowerPC 2.02 core
• eight fully functional coprocessors called Synergistic Processing Elements (SPEs)
• a specialized high-bandwidth circular data bus connecting the PPE, input/output elements, and the SPEs; this bus is called the Element Interconnect Bus (EIB)

To achieve the high performance needed for mathematically intensive tasks—such as decoding/encoding MPEG streams; generating or transforming three-dimensional data; and undertaking Fourier analysis of data—the Cell processor marries the SPEs and the PPE via an EIB to give access, via fully cache-coherent DMA (direct memory access), to both main memory and external data storage. To make the best of EIB—and to overlap computation and data transfer—each of the nine processing elements (i.e., PPE and SPEs) is equipped with a DMA engine. Since the SPE's load/store instructions can access only its own local scratchpad memory, each SPE depends entirely on DMA to transfer data to and from main memory and other SPEs' local memories. A DMA operation can transfer one or more blocks: either a single block up to 16 KB in size, or a list of 2 to 2048 such blocks. A major design decision in the Cell's architecture is the use of DMA as a central means of intra-chip data transfer, with the goal of enabling maximal asynchrony and concurrency in data processing inside a chip.

The PPE, which is capable of running a conventional operating system, has control over the SPEs; it can start, stop, interrupt, and schedule processes running on these SPEs. To this end, the PPE has additional instructions related to controlling the SPEs. Unlike SPEs, the PPE can read and write main memory and the local memories of SPEs through standard load/store instructions. The SPEs are not fully autonomous: they require priming by the PPE before they can do any useful work. Most of the system's power comes from the SPEs; therefore, the use of DMA for data transfer, along with the limited local memory footprint of each SPE, poses a major challenge to software developers wishing to make the most of the system's power. This situation demands careful hand-tuning of programs to extract maximal performance from this central processing unit (CPU).

The PPE-and-bus architecture includes various modes of operation, providing different levels of memory protection, thereby allowing areas of memory to be protected from access by specific processes running on the SPEs or the PPE.

Both the PPE and the SPE use reduced instruction set computer (RISC) architectures with a fixed-width 32-bit instruction format. The PPE contains a 64-bit general-purpose register (GPR) set, a 64-bit floating-point register (FPR) set, and a 128-bit AltiVec register set. The SPE contains 128-bit registers only. These can be used for one of two purposes: scalar data types ranging from 8 to 64 bits in size; or single instruction, multiple data (SIMD) computations on various integer and floating-point formats. System memory addresses for both the PPE and the SPE are expressed as 64-bit values. Local store addresses internal to the SPU (Synergistic Processor Unit) processor are expressed as a 32-bit word. In documentation relating to Cell, a word is always taken to mean 32 bits, a doubleword means 64 bits, and a quadword means 128 bits.

PowerXCell 8i

In 2008, IBM announced a variant of the Cell called the PowerXCell 8i, which is available in the QS22 blade server by IBM. The PowerXCell is manufactured on a 65 nm process; in addition, it adds support for up to 32 GB of slotted Double Data Rate 2 (DDR2) memory, as well as dramatically improving double-precision floating-point performance on the SPEs—from a peak of about 12.8 billion floating point operations per second (GFLOPS) to 102.4 GFLOPS total for eight SPEs; this is the same peak performance as that of the NEC SX-9 vector processor released around the same time. The IBM Roadrunner supercomputer, the world's fastest during 2008–2009, consisted of 12,240 PowerXCell 8i processors, along with 6,562 AMD Opteron processors. The PowerXCell-8i-powered supercomputers also dominated all of the top 6 "greenest" systems in the Green500 list, with the highest MFLOPS/watt ratio supercomputers in the world. In addition to use in the QS22 and supercomputers, the PowerXCell processor is also available as an accelerator on a PCI Express card, and it is used as the core processor in the QPACE supercomputer project.

Since the PowerXCell 8i removed the Rambus memory interface, in addition to adding significantly larger DDR2 memory interfaces and enhanced SPEs, the chip layout needed to be reworked; this resulted in a larger chip die and larger packaging.

Architecture

While the Cell chip can have a number of different configurations, the basic configuration is a multi-core chip composed of one Power Processing Element (PPE) (sometimes called "Processing Element" or "PE"), and multiple Synergistic Processing Elements (SPEs). The PPE and SPEs are linked together by an internal high-speed bus named "Element Interconnect Bus" (EIB).

Power Processing Element (PPE)

The PPE is the CPU core that is PowerPC-based, dual-issue, in-order, and two-way simultaneous-multithreaded; it has a 23-stage pipeline acting as the controller for eight SPEs, which handle most of the computational workload. The PPE has limited out-of-order execution capabilities; it can perform loads out of order and has delayed execution pipelines. The PPE will work with conventional operating systems because of its similarity to other 64-bit PowerPC processors, while the SPEs are designed for vectorized floating-point code execution. The PPE contains a 32-KiB, level-1 instruction cache; a 32-KiB, level-1 data cache; and a 512-KiB, level-2 cache. The size of a cache line is 128 bytes in all caches. Additionally, IBM has included the following elements:

• an AltiVec (VMX) unit which is fully pipelined for single-precision floating point (AltiVec 1 does not support double-precision floating-point vectors)
• 32-bit fixed-point Unit (FXU) with 64-bit register file per thread
• load-store Unit (LSU)
• 64-bit floating-point unit (FPU)
• branch unit (BRU)
• branch execution unit (BXU)

The PPE consists of three main units: an instruction unit (IU), an execution unit (XU), and a vector/scalar execution unit (VSU). The IU contains an L1 instruction cache, branch prediction hardware, instruction buffers, and dependency checking logic. The XU contains integer execution units (FXU) and a load-store unit (LSU). The VSU contains all of the execution resources for FPU and VMX. Each PPE can complete two double-precision operations per clock cycle using a scalar fused-multiply-add instruction, which translates to 6.4 GFLOPS at 3.2 GHz; or eight single-precision operations per clock cycle with a vector fused-multiply-add instruction, which translates to 25.6 GFLOPS at 3.2 GHz.

Xenon in Xbox 360

The PPE was designed specifically for the Cell processor, but during development, Microsoft approached IBM wanting a high-performance processor core for the Xbox 360. IBM agreed and built the tri-core Xenon processor, based on a slightly modified version of the PPE with added VMX128 extensions.

Synergistic Processing Element (SPE)

Each SPE is a dual-issue, in-order processor composed of a Synergistic Processing Unit (SPU) and a Memory Flow Controller (MFC) (DMA, MMU, and bus interface). SPEs have no branch prediction hardware (therefore a heavy burden falls on the compiler). Each SPE has six execution units divided among odd and even pipelines on each SPE: The SPU runs a specially developed instruction set architecture (ISA) with 128-bit SIMD organization for single- and double-precision instructions. With the current generation of the Cell, each SPE contains a 256-KiB embedded static random-access memory (SRAM) for instruction and data, called "Local Storage" (which is different from "Local Memory" in Sony's documents that refer to the video random-access memory [VRAM]); this is visible to the PPE and can be addressed directly by software. Each SPE can support up to 4 GiB of local store memory. The local store does not operate like a conventional CPU cache, since it is not transparent to software and does not contain hardware structures that predict which data to load. The SPEs contain a 128-bit, 128-entry register file and measure 14.5 mm² on a 90 nm process. An SPE can operate on sixteen 8-bit integers, eight 16-bit integers, four 32-bit integers, or four single-precision floating-point numbers in a single clock cycle, in addition to a memory operation. Critically, the SPU cannot directly access system memory; the 64-bit virtual memory addresses formed by the SPU must be passed from the SPU to the SPE's Memory Flow Controller to set up a DMA operation within the system address space.

In one typical usage scenario, the system will load the SPEs with small programs (similar to threads), chaining the SPEs together to handle each step of a complex operation. For instance, a set-top box might load programs for DVD reading; video and audio decoding; and display—then the data would be passed from SPE to SPE until finally ending up on the television. Another possibility is partitioning the input data set and having several SPEs perform the same kind of operation in parallel. At 3.2 GHz, each SPE gives a theoretical 25.6 GFLOPS of single-precision performance.

Compared to its personal-computer contemporaries, the relatively high overall floating-point performance of a Cell processor apparently dwarfs the capabilities of the SIMD unit in CPUs such as the Pentium 4 and the Athlon 64. However, comparing only the floating-point abilities of a system is a one-dimensional and application-specific metric. Unlike a Cell processor, such desktop CPUs are more suited to the general-purpose software usually run on personal computers. In addition to executing multiple instructions per clock, processors from Intel and AMD feature branch predictors. The Cell is designed to compensate for this through compiler assistance, in which prepare-to-branch instructions are created. For double-precision floating point operations, as sometimes used in personal computers and often used in scientific computing, Cell performance drops by an order of magnitude, but still reaches 20.8 GFLOPS (1.8 GFLOPS per SPE and 6.4 GFLOPS per PPE). The PowerXCell 8i variant, which was specifically designed for double precision, reaches 102.4 GFLOPS in double-precision calculations.

Tests by IBM show that the SPEs can reach 98% of their theoretical peak performance running optimized parallel matrix multiplication.

Toshiba has developed a coprocessor powered by four SPEs but no PPE, called the SpursEngine, which is designed to accelerate 3D and movie effects in consumer electronics.

Each SPE has a local memory of 256 KB. In total, the SPEs have 2 MB of local memory.

Element Interconnect Bus (EIB)

The EIB is a communication bus internal to the Cell processor that connects the various on-chip system elements: the PPE processor, the memory controller (MIC), the eight SPE coprocessors, and two off-chip I/O interfaces, for a total of twelve participants in the PlayStation 3 configuration. (The number of SPUs can vary in industrial applications.) The EIB also includes an arbitration unit, which functions as a set of traffic lights. In some documents, IBM refers to EIB participants as 'units'.

The EIB is implemented as a circular ring consisting of four 16-byte-wide unidirectional channels that counter-rotate in pairs. When traffic patterns permit, each channel can convey up to three transactions concurrently. As the EIB runs at half the system clock rate, the effective channel rate is 16 bytes every two system clock cycles. At maximum concurrency, with three active transactions on each of the four rings, the peak instantaneous EIB bandwidth is 96 bytes per clock cycle (12 concurrent transactions × 16 bytes wide / 2 system clock cycles per transfer). While this figure is often quoted in IBM literature, it is unrealistic to simply scale this number by processor clock speed. The arbitration unit imposes additional constraints.

IBM Senior Engineer David Krolak, lead designer of the EIB, explained the concurrency model as follows:

A ring can start a new op every three cycles. Each transfer always takes eight beats. That was one of the simplifications we made; it's optimized for streaming a lot of data. If you do small ops, it does not work quite as well. If you think of eight-car trains running around this track, as long as the trains aren't running into each other, they can coexist on the track.

Each participant on the EIB has one 16-byte read port and one 16-byte write port. The limit for a single participant is to read and write at a rate of 16 bytes per EIB clock cycle (for simplicity, often regarded as 8 bytes per system clock cycle). Each SPU processor contains a dedicated DMA management queue that is capable of scheduling long sequences of transactions to various endpoints without interfering with the SPU's ongoing computations; these DMA queues can be managed locally or remotely, providing additional flexibility in the control model.

Data flows on an EIB channel stepwise around the ring. Since there are twelve participants, the total number of steps around the channel back to the point of origin is twelve. Six steps is the longest distance between any pair of participants. An EIB channel is not permitted to convey data requiring more than six steps; such data must take the shorter route around the circle in the other direction. The number of steps involved in sending the packet has little impact on transfer latency: the clock speed driving the steps is fast relative to other considerations. However, longer communication distances are detrimental to the overall performance of the EIB because they reduce available concurrency.

Despite IBM's original desire to implement the EIB as a more powerful crossbar, the circular configuration that the company adopted to spare resources rarely represents a limiting factor on the performance of the Cell chip as a whole. In the worst case, the programmer must take extra care to schedule communication patterns where the EIB is able to function at high concurrency levels.

David Krolak explained this situation as follows:

Well, in the beginning, early in the development process, several people were pushing for a crossbar switch, and the way the bus is designed, you could actually pull out the EIB and put in a crossbar switch if you were willing to devote more silicon space on the chip to wiring. We had to find a balance between connectivity and area, and there just was not enough room to put a full crossbar switch in. So we came up with this ring structure, which we think is very interesting. It fits within the area constraints and still has very impressive bandwidth.

Bandwidth assessment

At 3.2 GHz, each channel flows at a rate of 25.6 GB/s. Viewing the EIB in isolation from the system elements that it connects, achieving twelve concurrent transactions at this flow rate results in an abstract EIB bandwidth of 307.2 GB/s. Based on this view, many IBM publications depict available EIB bandwidth as "greater than 300 GB/s". This number reflects the peak instantaneous EIB bandwidth scaled by processor frequency.

However, other technical restrictions are involved in the arbitration mechanism for packets accepted onto the bus. The IBM Systems Performance group explained as follows:

Each unit on the EIB can simultaneously send and receive 16 bytes of data every bus cycle. The maximum data bandwidth of the entire EIB is limited by the maximum rate at which addresses are snooped across all units in the system, which is one per bus cycle. Since each snooped address request can potentially transfer up to 128 bytes, the theoretical peak data bandwidth on the EIB at 3.2 GHz is 128Bx1.6 GHz = 204.8 GB/s.

This explanation apparently represents the full extent of IBM's public disclosure of this mechanism and its impact. Several topics—the EIB arbitration unit, the snooping mechanism, and interrupt generation on segment or page translation faults—are not well described in the documentation set as made public by IBM to date.

In practice, effective EIB bandwidth can also be limited by the ring participants involved. While each of the nine processing cores can sustain 25.6 GB/s read and write concurrently, the memory interface controller (MIC) is tied to a pair of XDR memory channels permitting a maximum flow of 25.6 GB/s for reads and writes combined; moreover, the two input/output (I/O) controllers are documented as supporting a peak combined input speed of 25.6 GB/s and a peak combined output speed of 35 GB/s.

To add to the confusion, some older publications cite EIB bandwidth assuming a 4 GHz system clock. This reference frame results in an instantaneous EIB bandwidth figure of 384 GB/s and an arbitration-limited bandwidth figure of 256 GB/s.

Everything considered, the theoretical 204.8 GB/s number (most often cited) is the best to keep in mind. The IBM Systems Performance group has demonstrated SPU-centric data flows achieving 197 GB/s on a Cell processor running at 3.2 GHz, showing this number is a fair reflection of practice.

Memory and I/O controllers

Cell contains a dual-channel Rambus XIO macro that interfaces to Rambus XDR memory. The memory interface controller (MIC) is separate from the XIO macro and is designed by IBM. The XIO-XDR link runs at 3.2 Gbit/s per pin. Two 32-bit channels can provide a theoretical maximum of 25.6 GB/s.

The I/O interface, also a Rambus design, is known as FlexIO. The FlexIO interface is organized into twelve lanes, each lane being a unidirectional 8-bit-wide point-to-point path. Five 8-bit-wide point-to-point paths are inbound lanes to Cell, while the remaining seven are outbound. This interface provides a theoretical peak bandwidth of 62.4 GB/s (36.4 GB/s outbound and 26 GB/s inbound) at 2.6 GHz. The FlexIO interface can be clocked independently, typically at 3.2 GHz. Four inbound and four outbound lanes support memory coherency.

Applications

Video processing card

Some companies, such as Leadtek, have released PCI Express cards based upon the Cell to allow for "faster than real time" transcoding of H.264, MPEG-2, and MPEG-4 video.

Blade server

On August 29, 2007, IBM announced the BladeCenter QS21 server. Generating a measured 1.05 billion floating point operations per second (gigaFLOPS) per watt, with peak performance of approximately 460 gigaFLOPS, it is one of the most power-efficient computing platforms to date. A single BladeCenter chassis can perform 6.4 trillion floating point operations per second (teraFLOPS) and more than 25.8 teraFLOPS in a standard 42U rack.

On May 13, 2008, IBM announced the BladeCenter QS22 server. The QS22 introduces the PowerXCell 8i processor with five times the double-precision floating-point performance of the QS21, as well as the capacity for up to 32 GB of DDR2 memory on-blade.

IBM has discontinued the Blade server line based on Cell processors as of January 12, 2012.

PCI Express board

Several companies provide PCI Express boards that use the IBM PowerXCell 8i. Their performance is reported as 179.2 GFLOPS (SP), 89.6 GFLOPS (DP) at 2.8 GHz.

Console video games

Sony's PlayStation 3 video game console was the first production application of the Cell processor, clocked at 3.2 GHz and containing seven out of eight operational SPEs, to allow Sony to increase the yield on processor manufacturing. Only six of the seven SPEs are accessible to developers, because one is reserved by the OS.

Because of its PlayStation 3 heritage, the Namco System 357 arcade hardware also used the Cell processor.

Home cinema

Toshiba has produced high-definition televisions (HDTVs) using Cell. The company presented a system to decode 48 standard definition MPEG-2 streams simultaneously on a 1920x1080 screen. This decoding can enable a viewer to choose a channel based on dozens of thumbnail videos displayed simultaneously on the screen.

Laptop PCs

Toshiba released the Qosmio G50 laptop in 2008, which contains embedded Cell technology. The laptop's CPU is otherwise an Intel Core x86-based chip, as is common in Toshiba computers.

Supercomputing

IBM's supercomputer, IBM Roadrunner, was a hybrid of general-purpose x86-64 Opteron processors and Cell processors. This system assumed the No. 1 spot on the June 2008 Top 500 list as the first supercomputer to run at petaFLOPS speeds, having achieved a sustained 1.026 petaFLOPS speed using the standard LINPACK benchmark. The IBM Roadrunner used the PowerXCell 8i version of the Cell processor; it was manufactured using 65 nm technology, and it contained enhanced SPUs that could handle double-precision calculations in the 128-bit registers, reaching double-precision 102 GFLOPs per chip.

Cluster computing

Clusters of PlayStation 3 (PS3) consoles are an attractive alternative to high-end systems based on Cell blades. Innovative Computing Laboratory—a group led by Jack Dongarra, in the Computer Science Department at the University of Tennessee—investigated such an application in depth. Terrasoft Solutions sells 8-node and 32-node PS3 clusters with Yellow Dog Linux pre-installed; these clusters are an implementation of Dongarra's research.

As first reported by Wired magazine on October 17, 2007, a novel application of using PS3s in a cluster configuration was implemented by Astrophysicist Gaurav Khanna from the Physics department of the University of Massachusetts Dartmouth; he replaced time on supercomputers with time on a cluster of eight PS3s instead. The next generation of this machine, called the PlayStation 3 Gravity Grid, uses a network of 16 machines and exploits the Cell processor for the target application—binary black-hole coalescence using perturbation theory. Specifically, the cluster performs astrophysical simulations of large supermassive black holes capturing smaller compact objects; it has generated numerical data that has been published multiple times in scientific research literature. The Cell processor version used by the PS3 has a main CPU and 6 SPEs available to the user, giving the Gravity Grid machine a total of 16 general-purpose processors and 96 vector processors. The machine has a one-time cost of $9,000 to build, and it is adequate for black-hole simulations that would otherwise cost $6,000 per run on a conventional supercomputer. The black-hole calculations are not memory-intensive and are highly localizable, and so they are well-suited to this architecture. Khanna claims that the cluster's performance exceeds that of a 100+ Intel Xeon core-based traditional Linux cluster in his simulations. The PS3 Gravity Grid gathered significant media attention in 2007, 2008, 2009, and 2010.

In 2007, the computational Biochemistry and Biophysics lab at the Universitat Pompeu Fabra (in Barcelona) deployed a Berkeley Open Infrastructure for Network Computing (BOINC) system called PS3GRID for collaborative computing based on the CellMD software, the first one designed specifically for the Cell processor.

The United States Air Force Research Laboratory has deployed a PlayStation 3 cluster of more than 1700 units, nicknamed the "Condor Cluster", for analyzing high-resolution satellite imagery. The Air Force claims that the Condor Cluster would be the 33rd largest supercomputer in the world in terms of capacity. The lab has opened up the supercomputer for use by universities for research purposes.

Distributed computing

With the help of the computing power of more than half a million PlayStation 3 consoles, the distributed computing project Folding@home has been recognized by Guinness World Records as the most powerful distributed network in the world. The first record was achieved on September 16, 2007, as the project surpassed one petaFLOPS, which had not been attained previously by a distributed computing network. In addition, the collective effort enabled the PS3s alone to reach the petaFLOPS mark on September 23, 2007. By comparison, the world's second-most powerful supercomputer at the time, IBM's Blue Gene/L, performed at about 478.2 teraFLOPS; this means that Folding@home's computing power is approximately twice that of Blue Gene/L (although the CPU interconnect in Blue Gene/L is more than one million times faster than the mean network speed in Folding@home). As of May 7, 2011, Folding@home runs at about 9.3 x86 petaFLOPS, with 26,000 active PS3s alone generating 1.6 petaFLOPS.

Mainframes

IBM announced on April 25, 2007, that it would begin integrating its microprocessors based on the Cell Broadband Engine Architecture into the company's System z line of mainframes. This work has resulted in a gameframe (a hybrid computer system).

Password cracking

The architecture of the Cell processor makes it better suited to hardware-assisted cryptographic brute-force attack applications than are conventional processors.

Software engineering

Because of the flexible nature of the Cell, there are several possibilities for using its resources, not limited to different computing paradigms.

Job queue

The PPE maintains a job queue, schedules jobs in SPEs, and monitors progress. Each SPE runs a "mini kernel" whose role is to fetch a job, execute it, and synchronize with the PPE.

Self-multitasking of SPEs

The mini-kernel and scheduling are distributed across SPEs. Tasks are synchronized using mutual exclusion (mutex) or semaphores, as in a conventional operating system. Ready-to-run tasks wait in a queue for an SPE to execute them. The SPEs use shared memory for all tasks in this configuration.

Stream processing

Each SPE runs a distinct program. Data comes from an input stream and is sent to SPEs. When an SPE has terminated processing, the output data is sent to an output stream.

This arrangement provides a flexible and powerful architecture for stream processing, and it allows explicit scheduling for each SPE separately. Other processors can also perform streaming tasks, but they are limited by the loaded kernel.

Open source software development

In 2005, patches enabling Cell support in the Linux kernel were submitted for inclusion by IBM developers. One of the patch developers, Arnd Bergmann, described the Linux-based Cell architecture at the LinuxTag 2005 conference. As of release 2.6.16 (on March 20, 2006), the Linux kernel officially supports the Cell processor.

The PPE and SPEs are programmable in C and C++ using a common API provided by libraries.

The company Fixstars Solutions provides Yellow Dog Linux for IBM and Mercury Cell-based systems, as well as for the PlayStation 3. Terra Soft strategically partnered with Mercury to provide a Linux Board Support Package for Cell, in addition to support and development of software applications on other Cell platforms; these included IBM's BladeCenter JS21 and Cell QS20, as well as Mercury Cell-based solutions. Terra Soft also maintains two toolsets: the Y-HPC (High-Performance Computing) Cluster Construction and Management Suite, and Y-Bio gene sequencing tools. Y-Bio is built upon the RPM Linux standard for package management, and it offers tools that help bioinformatics researchers perform their work more efficiently. IBM has developed a pseudo-filesystem for Linux called "spufs" (as in 'SPU filesystem'; cf. the "procfs" process filesystem); it simplifies access to and use of SPE resources. IBM maintains Linux kernel and GDB ports, while Sony maintains the GNU toolchain (GCC and binutils).

In November 2005, IBM released the "Cell Broadband Engine (CBE) Software Development Kit Version 1.0"—consisting of a simulator and assorted tools—to its website. Development versions of the latest kernel and tools for the Fedora Core 4 Linux distribution are maintained at the Barcelona Supercomputing Center website.

In August 2007, Mercury Computer Systems released an SDK for the PlayStation 3 to support high-performance computing.

In November 2007, Fixstars Corporation released the new "CVCell" module, aiming to accelerate several important OpenCV APIs for Cell. In a series of software calculation tests, the company recorded execution times on a 3.2 GHz Cell processor that were between 6 and 27 times faster than the same software running on a 2.4 GHz Intel Core 2 Duo processor.

In October 2009, IBM released an OpenCL driver for the POWER6 processor and the CBE. This driver allows programs written in the cross-platform API to be run easily on Cell PSE.